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1996 microchip technology inc. ds30412c-page 1 devices included in this data sheet: pic17cr42 pic17c42a pic17c43 pic17cr43 pic17c44 pic17c42? microcontroller core features: only 58 single word instructions to learn all single cycle instructions (121 ns) except for program branches and table reads/writes which are two-cycle operating speed: - dc - 33 mhz clock input - dc - 121 ns instruction cycle hardware multiplier (not available on the pic17c42) interrupt capability 16 levels deep hardware stack direct, indirect and relative addressing modes internal/external program memory execution 64k x 16 addressable program memory space peripheral features: 33 i/o pins with individual direction control high current sink/source for direct led drive - ra2 and ra3 are open drain, high voltage (12v), high current (60 ma), i/o two capture inputs and two pwm outputs - captures are 16-bit, max resolution 160 ns - pwm resolution is 1- to 10-bit tmr0: 16-bit timer/counter with 8-bit programma- ble prescaler tmr1: 8-bit timer/counter device program memory data memory eprom rom pic17cr42 - 2k 232 pic17c42a 2k - 232 pic17c43 4k - 454 pic17cr43 - 4k 454 pic17c44 8k - 454 pic17c42? 2k - 232 o o pin diagram tmr2: 8-bit timer/counter tmr3: 16-bit timer/counter universal synchronous asynchronous receiver transmitter (usart/sci) special microcontroller features: power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation code-protection power saving sleep mode selectable oscillator options cmos technology: low-power, high-speed cmos eprom/rom technology fully static design wide operating voltage range (2.5v to 6.0v) commercial and industrial temperature range low-power consumption - < 5 ma @ 5v, 4 mhz - 100 m a typical @ 4.5v, 32 khz - < 1 m a typical standby current @ 5v pic17c4x rd0/ad8 rd1/ad9 rd2/ad10 rd3/ad11 rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 mclr /v pp v ss re0/ale re1/oe re2/wr test ra0/int ra1/t0cki ra2 ra3 ra4/rx/dt ra5/tx/ck v dd rc0/ad0 rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 v ss rb0/cap1 rb1/cap2 rb2/pwm1 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb6 rb7 osc1/clkin osc2/clkout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pdip, cerdip, windowed cerdip pic17c4x high-performance 8-bit cmos eprom/rom microcontroller ?not recommended for new designs, use 17c42a. this document was created with framemake r404
pic17c4x ds30412c-page 2 1996 microchip technology inc. pin diagrams cont.d rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 mclr /v pp v ss v ss re0/ale re1/oe re2/wr test rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 v ss v ss rb0/cap1 rb1/cap2 rb2/pwm1 rb3/pwm2 rb4/tclk12 rc3/ad3 rc2/ad2 rc1/ad1 rc0/ad0 nc v dd v dd rd0/ad8 rd1/ad9 rd2/ad10 rd3/ad11 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 ra0/int ra1/t0cki ra2 ra3 ra4/rx/dt ra5/tx/ck osc2/clkout osc1/clkin rb7 rb6 rb5/tclk3 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 rb4/tclk12 rb3/pwm2 rb2/pwm1 rb1/cap2 rb0/cap1 v ss v ss rc7/ad7 rc6/ad6 rc5/ad5 rc4/ad4 test re2/wr re1/oe re0/ale v ss v ss mclr /v pp rd7/ad15 rd6/ad14 rd5/ad13 rd4/ad12 ra0/int ra1/t0cki ra2 ra3 ra4/rx/dt ra5/tx/ck osc2/clkout osc1/clkin rb7 rb6 rb5/tclk3 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 rc3/ad3 rc2/ad2 rc1/ad1 rc0/ad0 nc v dd v dd rd0/ad8 rd1/ad9 rd2/ad10 rd3/ad11 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 plcc mqfp tqfp all devices are available in all package types, listed in section 21.0, with the following exceptions: rom devices are not available in windowed cerdip packages tqfp is not available for the pic17c42. pic17c4x pic17c4x
1996 microchip technology inc. ds30412c-page 3 pic17c4x table of contents 1.0 overview .............................................................................................................................................................. 5 2.0 pic17c4x device varieties ................................................................................................................................. 7 3.0 architectural overview ......................................................................................................................................... 9 4.0 reset .................................................................................................................................................................. 15 5.0 interrupts ............................................................................................................................................................ 21 6.0 memory organization ......................................................................................................................................... 29 7.0 table reads and table writes........................................................................................................................... 43 8.0 hardware multiplier ............................................................................................................................................ 49 9.0 i/o ports ............................................................................................................................................................. 53 10.0 overview of timer resources ............................................................................................................................ 65 11.0 timer0 ................................................................................................................................................................ 67 12.0 timer1, timer2, timer3, pwms and captures................................................................................................... 71 13.0 universal synchronous asynchronous receiver transmitter (usart) module................................................ 83 14.0 special features of the cpu.............................................................................................................................. 99 15.0 instruction set summary .................................................................................................................................. 107 16.0 development support....................................................................................................................................... 143 17.0 pic17c42 electrical characteristics ................................................................................................................ 147 18.0 pic17c42 dc and ac characteristics............................................................................................................. 163 19.0 pic17cr42/42a/43/r43/44 electrical characteristics..................................................................................... 175 20.0 pic17cr42/42a/43/r43/44 dc and ac characteristics ................................................................................. 193 21.0 packaging information...................................................................................................................................... 205 appendix a: modifications .......................................................................................................................................... 211 appendix b: compatibility........................................................................................................................................... 211 appendix c: what? new ............................................................................................................................................ 212 appendix d: what? changed..................................................................................................................................... 212 appendix e: pic16/17 microcontrollers ...................................................................................................................... 213 appendix f: errata for pic17c42 silicon ................................................................................................................... 223 index ............................................................................................................................................................................ 226 pic17c4x product identification system .................................................................................................................... 237 for register and module descriptions in this data sheet, device legends show which devices apply to those sections. for example, the legend below shows that some features of only the pic17c43, pic17cr43, pic17c44 are described in this section. applicable devices 42 r42 42a 43 r43 44 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an excep- tional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error from the previous version of the pic17c4x data sheet (literature number ds30412b), please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document. to assist you in the use of this document, appendix c contains a list of new information in this data sheet, while appendix d contains information that has changed
pic17c4x ds30412c-page 4 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 5 pic17c4x 1.0 overview this data sheet covers the pic17c4x group of the pic17cxx family of microcontrollers. the following devices are discussed in this data sheet: pic17c42 pic17cr42 pic17c42a pic17c43 pic17cr43 pic17c44 the pic17cr42, pic17c42a, pic17c43, pic17cr43, and pic17c44 devices include architec- tural enhancements over the pic17c42. these enhancements will be discussed throughout this data sheet. the pic17c4x devices are 40/44-pin, eprom/rom-based members of the versatile pic17cxx family of low-cost, high-performance, cmos, fully-static, 8-bit microcontrollers. all pic16/17 microcontrollers employ an advanced risc architecture. the pic17cxx has enhanced core features, 16-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 16-bit wide instruction word with a separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). a total of 55 instructions (reduced instruction set) are available in the pic17c42 and 58 instructions in all the other devices. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. for mathematical intensive applica- tions all devices, except the pic17c42, have a single cycle 8 x 8 hardware multiplier. pic17cxx microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. pic17c4x devices have up to 454 bytes of ram and 33 i/o pins. in addition, the pic17c4x adds several peripheral features useful in many high performance applications including: four timer/counters two capture inputs two pwm outputs a universal synchronous asynchronous receiver transmitter (usart) these special features reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lf oscillator is for low frequency crystals and minimizes power consumption, xt is a standard crystal, and the ec is for external clock input. the sleep (power-down) mode offers additional power saving. the user can wake-up the chip from sleep through several external and internal interrupts and device resets. there are four con?uration options for the device oper- ational modes: microprocessor microcontroller extended microcontroller protected microcontroller the microprocessor and extended microcontroller modes allow up to 64k-words of external program memory. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software mal- function. table 1-1 lists the features of the pic17c4x devices. a uv-erasable cerdip-packaged version is ideal for code development while the cost-effective one-time programmable (otp) version is suitable for production in any volume. the pic17c4x ?s perfectly in applications ranging from precise motor control and industrial process con- trol to automotive, instrumentation, and telecom appli- cations. other applications that require extremely fast execution of complex software programs or the ?xibil- ity of programming the software code as one of the last steps of the manufacturing process would also be well suited. the eprom technology makes customization of application programs (with unique security codes, combinations, model numbers, parameter storage, etc.) fast and convenient. small footprint package options make the pic17c4x ideal for applications with space limitations that require high performance. high speed execution, powerful peripheral features, ?xible i/o, and low power consumption all at low cost make the pic17c4x ideal for a wide range of embedded con- trol applications. 1.1 f amil y and upwar d compatibility those users familiar with the pic16c5x and pic16cxx families of microcontrollers will see the architectural enhancements that have been imple- mented. these enhancements allow the device to be more ef?ient in software and hardware requirements. please refer to appendix a for a detailed list of enhancements and modi?ations. code written for pic16c5x or pic16cxx can be easily ported to pic17cxx family of devices (appendix b). 1.2 de velopment suppor t the pic17cxx family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a universal programmer, a ? compiler, and fuzzy logic support tools. this document was created with framemake r404
pic17c4x ds30412c-page 6 1996 microchip technology inc. table 1-1: pic17cxx family of devices features pic17c42 pic17cr42 pic17c42a pic17c43 pic17cr43 pic17c44 maximum frequency of operation 25 mhz 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz operating voltage range 4.5 - 5.5v 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v program memory x16 (eprom) 2k - 2k 4k - 8k (rom)-2k- -4k- data memory (bytes) 232 232 232 454 454 454 hardware multiplier (8 x 8) - yes yes yes yes yes timer0 (16-bit + 8-bit postscaler) yes yes yes yes yes yes timer1 (8-bit) yes yes yes yes yes yes timer2 (8-bit) yes yes yes yes yes yes timer3 (16-bit) yes yes yes yes yes yes capture inputs (16-bit) 222222 pwm outputs (up to 10-bit) 222222 usart/sci yes yes yes yes yes yes power-on reset yes yes yes yes yes yes watchdog timer yes yes yes yes yes yes external interrupts yes yes yes yes yes yes interrupt sources 11 11 11 11 11 11 program memory code protect yes yes yes yes yes yes i/o pins 33 33 33 33 33 33 i/o high current capabil- ity source 25 ma 25 ma 25 ma 25 ma 25 ma 25 ma sink 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) package types 40-pin dip 44-pin plcc 44-pin mqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp note 1: pins ra2 and ra3 can sink up to 60 ma.
1996 microchip technology inc. ds30412c-page 7 pic17c4x 2.0 pic17c4x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic17c4x product selec- tion system section at the end of this data sheet. when placing orders, please use the ?ic17c4x product identi?ation system at the back of this data sheet to specify the correct part number. for the pic17c4x family of devices, there are four device ?ypes as indicated in the device number: 1. c , as in pic17 c 42. these devices have eprom type memory and operate over the standard voltage range. 2. lc , as in pic17 lc 42. these devices have eprom type memory, operate over an extended voltage range, and reduced frequency range. 3. cr , as in pic17 cr 42. these devices have rom type memory and operate over the stan- dard voltage range. 4. lcr , as in pic17 lcr 42. these devices have rom type memory, operate over an extended voltage range, and reduced frequency range. 2.1 uv erasab le de vices the uv erasable version, offered in cerdip package, is optimal for prototype development and pilot pro- grams. the uv erasable version can be erased and repro- grammed to any of the con?uration modes. microchip's pro mate programmer supports pro- gramming of the pic17c4x. third party programmers also are available; refer to the third party guide for a list of sources. 2.2 one-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the con?uration bits must also be programmed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and con?uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before produc- tion shipments are available. please contact your local microchip technology sales of?e for more details. 2.4 serializ ed quic k-t urnar ound pr oduction (sqtp sm ) de vices microchip offers a unique programming service where a few user-de?ed locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number. rom devices do not allow serialization information in the program memory space. for information on submitting rom code, please con- tact your regional sales of?e. 2.5 read onl y memor y (r om) de vices microchip offers masked rom versions of several of the highest volume parts, thus giving customers a low cost option for high volume, mature products. for information on submitting rom code, please con- tact your regional sales of?e. this document was created with framemake r404
pic17c4x ds30412c-page 8 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 9 pic17c4x 3.0 architectural overview the high performance of the pic17c4x can be attrib- uted to a number of architectural features commonly found in risc microprocessors. to begin with, the pic17c4x uses a modi?d harvard architecture. this architecture has the program and data accessed from separate memories. so the device has a program memory bus and a data memory bus. this improves bandwidth over traditional von neumann architecture, where program and data are fetched from the same memory (accesses over the same bus). separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. pic17c4x opcodes are 16-bits wide, enabling single word instructions. the full 16-bit wide program memory bus fetches a 16-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions. consequently, all instructions execute in a single cycle (121 ns @ 33 mhz), except for program branches and two special instructions that transfer data between program and data memory. the pic17c4x can address up to 64k x 16 of program memory space. the pic17c42 and pic17c42a integrate 2k x 16 of eprom program memory on-chip, while the pic17cr42 has 2k x 16 of rom program memory on- chip. the pic17c43 integrates 4k x 16 of eprom program memory, while the pic17cr43 has 4k x 16 of rom program memory. the pic17c44 integrates 8k x 16 eprom program memory. program execution can be internal only (microcontrol- ler or protected microcontroller mode), external only (microprocessor mode) or both (extended microcon- troller mode). extended microcontroller mode does not allow code protection. the pic17cxx can directly or indirectly address its register ?es or data memory. all special function regis- ters, including the program counter (pc) and working register (wreg), are mapped in the data memory. the pic17cxx has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal sit- uations make programming with the pic17cxx simple yet ef?ient. in addition, the learning curve is reduced signi?antly. one of the pic17cxx family architectural enhance- ments from the pic16cxx family allows two ?e regis- ters to be used in some two operand instructions. this allows data to be moved directly between two registers without going through the wreg register. this increases performance and decreases program mem- ory usage. the pic17cxx devices contain an 8-bit alu and work- ing register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, sub- traction, shift, and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. the wreg register is an 8-bit working register used for alu operations. all pic17c4x devices (except the pic17c42) have an 8 x 8 hardware multiplier. this multiplier generates a 16-bit result in a single cycle. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borro w and digit borro w out bit, respec- tively, in subtraction. see the sublw and subwf instructions for examples. although the alu does not perform signed arithmetic, the over?w bit (ov) can be used to implement signed math. signed arithmetic is comprised of a magnitude and a sign bit. the over?w bit indicates if the magni- tude over?ws and causes the sign bit to change state. signed math can have greater than 7-bit values (mag- nitude), if more than one byte is used. the use of the over?w bit only operates on bit6 (msb of magnitude) and bit7 (sign bit) of the value in the alu. that is, the over?w bit is not useful if trying to implement signed math where the magnitude, for example, is 11-bits. if the signed math values are greater than 7-bits (15-, 24- or 31-bit), the algorithm must ensure that the low order bytes ignore the over?w status bit. care should be taken when adding and subtracting signed numbers to ensure that the correct operation is executed. example 3-1 shows an item that must be taken into account when doing signed arithmetic on an alu which operates as an unsigned machine. example 3-1: signed math signed math requires the result in reg to be feh (-126). this would be accomplished by subtracting one as opposed to adding one. simpli?d block diagrams are shown in figure 3-1 and figure 3-2. the descriptions of the device pins are listed in table 3-1. hex value signed value math unsigned value math ffh + 01h = ? -127 + 1 = -126 (feh) 255 + 1 = 0 (00h); carry bit = 1 this document was created with framemake r404
pic17c4x ds30412c-page 10 1996 microchip technology inc. figure 3-1: pic17c42 block diagram clock generator power on reset watchdog timer osc startup timer test mode select system data latch address latch program memory (eprom/rom) table ptr<16> stack 16 x 16 pch pcl pclath<8> table latch <16> rom latch <16> literal instruction decoder control outputs ir latch <16> fsr0 fsr1 8 8 8 ir bus <16> ram addr buffer data latch read/write decode for registers mapped in data space wreg <8> bitop alu shifter ir bus <16> portb porta rb0/cap1 rb1/cap2 rb2/pwm1 rb2/pwm2 rb4/tclk12 rb5/tclk3 rb6 rb7 ra0/int ra1/t0cki ra2 ra3 ra4/rx/dt ra5/tx/ck ra1/ timer1, timer2, timer3 capture pwm digital i/o ports a, b serial port timer0 module data bus <8> ir bus <7:0> ra1/t0cki ra0/int 86 8 6 2 6 4 3 ir <2:0> data bus <8> control signals to cpu chip_reset and other control signals q1, q2, q3, q4 16 16 11 ad <15:0> portc and ale, wr , oe porte osc1, osc2 v dd , v ss mclr /v pp test decode bsr interrupt module 8 rdf wrf t0cki peripherals ir <7> bus inter- face 16 data ram 232x8 2k x 16 portd
1996 microchip technology inc. ds30412c-page 11 pic17c4x figure 3-2: pic17cr42/42a/43/r43/44 block diagram clock generator power on reset watchdog timer osc startup timer test mode select system data latch address latch program memory (eprom/rom) table ptr<16> stack 16 x 16 pch pcl pclath<8> table latch <16> rom latch <16> literal instruction decoder control outputs ir latch <16> fsr0 fsr1 8 8 8 ir bus <16> ram addr buffer data latch read/write decode for registers mapped in data space wreg <8> bitop alu shifter ir bus <16> portb porta rb0/cap1 rb1/cap2 rb2/pwm1 rb2/pwm2 rb4/tclk12 rb5/tclk3 rb6 rb7 ra0/int ra1/t0cki ra2 ra3 ra4/rx/dt ra5/tx/ck ra1/ timer1, timer2, timer3 capture pwm digital i/o ports a, b serial port timer0 module data bus <8> bsr<7:4> ra1/t0cki ra0/int 86 8 6 2 6 4 3 ir <2:0> data bus <8> control signals to cpu chip_reset and other control signals q1, q2, q3, q4 16 16 13 ad <15:0> portc and ale, wr , oe porte osc1, osc2 v dd , v ss mclr /v pp test decode bsr interrupt module 12 rdf wrf t0cki peripherals ir <7> bus inter- face 16 8 x 8 mult prodh prodl data ram 454 x 8 pic17c43 8k x 16 - pic17c44 4k x 16 - pic17c43 ir bus<7:0> 4k x 16 - pic17cr43 454 x 8 pic17cr43 454 x 8 pic17c44 232 x 8 pic17c42a 232 x 8 pic17cr42 2k x 16 - pic17c42a 2k x 16 - pic17cr42 portd
pic17c4x ds30412c-page 12 1996 microchip technology inc. table 3-1: pinout descriptions name dip no. plcc no. qfp no. i/o/p type buffer type description osc1/clkin 19 21 37 i st oscillator input in crystal/resonator or rc oscillator mode. external clock input in external clock mode. osc2/clkout 20 22 38 o oscillator output. connects to crystal or resonator in crystal oscillator mode. in rc oscillator or external clock modes osc2 pin outputs clkout which has one fourth the fre- quency of osc1 and denotes the instruction cycle rate. mclr /v pp 32 35 7 i/p st master clear (reset) input/programming voltage (v pp ) input. this is the active low reset input to the chip. porta is a bi-directional i/o port except for ra0 and ra1 which are input only. ra0/int 26 28 44 i st ra0/int can also be selected as an external interrupt input. interrupt can be con?ured to be on positive or negative edge. ra1/t0cki 25 27 43 i st ra1/t0cki can also be selected as an external interrupt input, and the interrupt can be con?ured to be on posi- tive or negative edge. ra1/t0cki can also be selected to be the clock input to the timer0 timer/counter. ra2 24 26 42 i/o st high voltage, high current, open drain input/output port pins. ra3 23 25 41 i/o st high voltage, high current, open drain input/output port pins. ra4/rx/dt 22 24 40 i/o st ra4/rx/dt can also be selected as the usart (sci) asynchronous receive or usart (sci) synchronous data. ra5/tx/ck 21 23 39 i/o st ra5/tx/ck can also be selected as the usart (sci) asynchronous transmit or usart (sci) synchronous clock. portb is a bi-directional i/o port with software con?urable weak pull-ups. rb0/cap1 11 13 29 i/o st rb0/cap1 can also be the cap1 input pin. rb1/cap2 12 14 30 i/o st rb1/cap2 can also be the cap2 input pin. rb2/pwm1 13 15 31 i/o st rb2/pwm1 can also be the pwm1 output pin. rb3/pwm2 14 16 32 i/o st rb3/pwm2 can also be the pwm2 output pin. rb4/tclk12 15 17 33 i/o st rb4/tclk12 can also be the external clock input to timer1 and timer2. rb5/tclk3 16 18 34 i/o st rb5/tclk3 can also be the external clock input to timer3. rb6 17 19 35 i/o st rb7 18 20 36 i/o st portc is a bi-directional i/o port. rc0/ad0 2 3 19 i/o ttl this is also the lower half of the 16-bit wide system bus in microprocessor mode or extended microcontroller mode. in multiplexed system bus con?uration, these pins are address output as well as data input or output. rc1/ad1 3 4 20 i/o ttl rc2/ad2 4 5 21 i/o ttl rc3/ad3 5 6 22 i/o ttl rc4/ad4 6 7 23 i/o ttl rc5/ad5 7 8 24 i/o ttl rc6/ad6 8 9 25 i/o ttl rc7/ad7 9 10 26 i/o ttl legend: i = input only; o = output only; i/o = input/output; p = power; ?= not used; ttl = ttl input; st = schmitt trigger input.
1996 microchip technology inc. ds30412c-page 13 pic17c4x portd is a bi-directional i/o port. rd0/ad8 40 43 15 i/o ttl this is also the upper byte of the 16-bit system bus in microprocessor mode or extended microprocessor mode or extended microcontroller mode. in multiplexed system bus con?uration these pins are address output as well as data input or output. rd1/ad9 39 42 14 i/o ttl rd2/ad10 38 41 13 i/o ttl rd3/ad11 37 40 12 i/o ttl rd4/ad12 36 39 11 i/o ttl rd5/ad13 35 38 10 i/o ttl rd6/ad14 34 37 9 i/o ttl rd7/ad15 33 36 8 i/o ttl porte is a bi-directional i/o port. re0/ale 30 32 4 i/o ttl in microprocessor mode or extended microcontroller mode, it is the address latch enable (ale) output. address should be latched on the falling edge of ale output. re1/oe 29 31 3 i/o ttl in microprocessor or extended microcontroller mode, it is the output enable (oe ) control output (active low). re2/wr 28 30 2 i/o ttl in microprocessor or extended microcontroller mode, it is the write enable (wr ) control output (active low). test 27 29 1 i st test mode selection control input. always tie to v ss for nor- mal operation. v ss 10, 31 11, 12, 33, 34 5, 6, 27, 28 p ground reference for logic and i/o pins. v dd 1 1, 44 16, 17 p positive supply for logic and i/o pins. table 3-1: pinout descriptions name dip no. plcc no. qfp no. i/o/p type buffer type description legend: i = input only; o = output only; i/o = input/output; p = power; ?= not used; ttl = ttl input; st = schmitt trigger input.
pic17c4x ds30412c-page 14 1996 microchip technology inc. 3.1 cloc king sc heme/instruction cyc le the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3, and q4. internally, the pro- gram counter (pc) is incremented every q1, and the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w are shown in figure 3-3. 3.2 instruction flo w/pipelining an ?nstruction cycle consists of four q cycles (q1, q2, q3, and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ) then two cycles are required to complete the instruction (example 3-2). a fetch cycle begins with the program counter incre- menting in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-3: clock/instruction cycle example 3-2: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed from the pipeline while the new instruction is being fetched and then executed. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
1996 microchip technology inc. ds30412c-page 15 pic17c4x 4.0 reset the pic17cxx differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation wdt reset (normal operation) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are forced to a ?eset state on power-on reset (por), on mclr or wdt reset and on m clr reset during sleep. they are not affected by a wdt reset during sleep, since this reset is viewed as the resumption of normal operation. the t o and pd bits are set or cleared differently in different reset situations as indicated in table 4-3. these bits are used in software to determine the nature of reset. see table 4-4 for a full description of reset states of all reg- isters. a simpli?d block diagram of the on-chip reset circuit is shown in figure 4-1. note: while the device is in a reset state, the internal phase clock is held in the q1 state. any processor mode that allows external execution will force the re0/ale pin as a low output and the re1/oe and re2/wr pins as high outputs. 4.1 p o w e r -on reset (por), p o wer -up ti m er (pwr t) , and oscillator star t-up timer (ost) 4.1.1 power-on reset (por) the power-on reset circuit holds the device in reset until v dd is above the trip point (in the range of 1.4v - 2.3v). the pic17c42 does not produce an internal reset when v dd declines. all other devices will produce an internal reset for both rising and falling v dd . to take advantage of the por, just tie the mclr /v pp pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create power-on reset. a minimum rise time for v dd is required. see electrical speci?ations for details. 4.1.2 power-up timer (pwrt) the power-up timer provides a ?ed 96 ms time-out (nominal) on power-up. this occurs from rising edge of the por signal and after the ?st rising edge of mclr (detected high). the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. in most cases the pwrt delay allows the v dd to rise to an acceptable level. the power-up time delay will vary from chip to chip and to v dd and temperature. see dc parameters for details. figure 4-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc? wdt time_out power_on_reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter power_up (enable the pwrt timer only during power_up) (power_up + wake_up) (xt + lf) (enable the ost if it is power_up or wake_up from sleep and osc type is xt or lf) reset enable ost enable pwrt ? this rc oscillator is shared with the wdt when not in a power-up sequence. this document was created with framemake r404
pic17c4x ds30412c-page 16 1996 microchip technology inc. 4.1.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (1024t osc ) delay after mclr is detected high or a wake-up from sleep event occurs. the ost time-out is invoked only for xt and lf oscilla- tor modes on a power-on reset or a wake-up from sleep. the ost counts the oscillator pulses on the osc1/clkin pin. the counter only starts incrementing after the amplitude of the signal reaches the oscillator input thresholds. this delay allows the crystal oscillator or resonator to stabilize before the device exits reset. the length of time-out is a function of the crystal/reso- nator frequency. 4.1.4 time-out sequence on power-up the time-out sequence is as follows: first the internal por signal goes high when the por trip point is reached. if mclr is high, then both the ost and pwrt timers start. in general the pwrt time-out is longer, except with low frequency crystals/resona- tors. the total time-out also varies based on oscillator con?uration. table 4-1 shows the times that are asso- ciated with the oscillator con?uration. figure 4-2 and figure 4-3 display these time-out sequences. if the device voltage is not within electrical speci?ation at the end of a time-out, the mclr /v pp pin must be held low until the voltage is within the device speci?a- tion. the use of an external rc delay is suf?ient for many of these applications. table 4-1: time-out in various situations the time-out sequence begins from the ?st rising edge of mclr . table 4-3 shows the reset conditions for some special registers, while table 4-4 shows the initialization condi- tions for all the registers. the shaded registers (in table 4-4) are for all devices except the pic17c42. in the pic17c42, the prodh and prodl registers are general purpose ram. table 4-2: status bits and their significance in figure 4-2, figure 4-3 and figure 4-4, t pwrt > t ost , as would be the case in higher frequency crys- tals. for lower frequency crystals, (i.e., 32 khz) t ost would be greater. oscillator con?uration power-up wake up from sleep mclr reset xt, lf greater of: 96 ms or 1024t osc 1024t osc ec, rc greater of: 96 ms or 1024t osc t o pd event 11 power-on reset, mclr reset during normal operation, or clrwdt instruction executed 10 mclr reset during sleep or interrupt wake-up from sleep 01 wdt reset during normal operation 00 wdt reset during sleep table 4-3: reset condition for the program counter and the cpusta register event pch:pcl cpusta ost active power-on reset 0000h --11 11-- ye s mclr reset during normal operation 0000h --11 11-- no mclr reset during sleep 0000h --11 10-- yes (2) wdt reset during normal operation 0000h --11 01-- no wdt reset during sleep (3) 0000h --11 00-- yes (2) interrupt wake-up from sleep glintd is set pc + 1 --11 10-- yes (2) glintd is clear pc + 1 (1) --10 10-- yes (2) legend: u = unchanged, x = unknown, - = unimplemented read as '0'. note 1: on wake-up, this instruction is executed. the instruction at the appropriate interrupt vector is fetched and then executed. 2: the ost is only active when the oscillator is con?ured for xt or lf modes. 3: the program counter = 0, that is the device branches to the reset vector. this is different from the mid-range devices.
1996 microchip technology inc. ds30412c-page 17 pic17c4x figure 4-2: time-out sequence on power-up (mclr tied to v dd ) figure 4-3: time-out sequence on power-up (mclr not tied to v dd ) figure 4-4: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
pic17c4x ds30412c-page 18 1996 microchip technology inc. figure 4-5: oscillator start-up time figure 4-6: using on-chip por figure 4-7: brown-out protection circuit 1 v dd mclr osc2 ost time_out pwrt time_out internal reset t osc 1 t ost t pwrt this ?ure shows in greater detail the timings involved with the oscillator start-up timer. in this example the low frequency crystal start-up time is larger than power-up time (t pwrt ). tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the oscillator start-up timer (ost). t ost = 1024t osc . v dd mclr pic17cxx v dd this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. v dd 33k 10k 40 k w v dd mclr pic17cxx figure 4-8: pic17c42 external power-on reset circuit (for slow v dd power-up) figure 4-9: brown-out protection circuit 2 note 1: an external power-on reset circuit is required only if v dd power-up time is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to ensure that the voltage drop across r does not exceed 0.2v (max. leakage current spec. on the mclr /v pp pin is 5 m a). a larger voltage drop will degrade v ih level on the mclr /v pp pin. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capaci- tor c in the event of mclr /v pp pin breakdown due to electrostatic dis- charge (esd) or (electrical overstress) eos. c r1 r d v dd mclr pic17c42 v dd this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd r1 r1 + r2 = 0.7v r2 40 k w v dd mclr pic17cxx r1 q1 v dd
1996 microchip technology inc. ds30412c-page 19 pic17c4x table 4-4: initialization conditions for special function registers register address power-on reset mclr reset wdt reset wake-up from sleep through interrupt unbanked indf0 00h 0000 0000 0000 0000 0000 0000 fsr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000h 0000h pc + 1 (2) pclath 03h 0000 0000 0000 0000 uuuu uuuu alusta 04h 1111 xxxx 1111 uuuu 1111 uuuu t0sta 05h 0000 000- 0000 000- 0000 000- cpusta (3) 06h --11 11-- --11 qq-- --uu qq-- intsta 07h 0000 0000 0000 0000 uuuu uuuu (1) indf1 08h 0000 0000 0000 0000 uuuu uuuu fsr1 09h xxxx xxxx uuuu uuuu uuuu uuuu wreg 0ah xxxx xxxx uuuu uuuu uuuu uuuu tmr0l 0bh xxxx xxxx uuuu uuuu uuuu uuuu tmr0h 0ch xxxx xxxx uuuu uuuu uuuu uuuu tblptrl (4) 0dh xxxx xxxx uuuu uuuu uuuu uuuu tblptrh (4) 0eh xxxx xxxx uuuu uuuu uuuu uuuu tblptrl (5) 0dh 0000 0000 0000 0000 uuuu uuuu tblptrh (5) 0eh 0000 0000 0000 0000 uuuu uuuu bsr 0fh 0000 0000 0000 0000 uuuu uuuu bank 0 porta 10h 0-xx xxxx 0-uu uuuu uuuu uuuu ddrb 11h 1111 1111 1111 1111 uuuu uuuu portb 12h xxxx xxxx uuuu uuuu uuuu uuuu rcsta 13h 0000 -00x 0000 -00u uuuu -uuu rcreg 14h xxxx xxxx uuuu uuuu uuuu uuuu txsta 15h 0000 --1x 0000 --1u uuuu --uu txreg 16h xxxx xxxx uuuu uuuu uuuu uuuu spbrg 17h xxxx xxxx uuuu uuuu uuuu uuuu bank 1 ddrc 10h 1111 1111 1111 1111 uuuu uuuu portc 11h xxxx xxxx uuuu uuuu uuuu uuuu ddrd 12h 1111 1111 1111 1111 uuuu uuuu portd 13h xxxx xxxx uuuu uuuu uuuu uuuu ddre 14h ---- -111 ---- -111 ---- -uuu porte 15h ---- -xxx ---- -uuu ---- -uuu pir 16h 0000 0010 0000 0010 uuuu uuuu (1) pie 17h 0000 0000 0000 0000 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. note 1: one or more bits in intsta, pir will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the glintd bit is cleared, the pc is loaded with the interrupt vector. 3: see table 4-3 for reset value of speci? condition. 4: only applies to the pic17c42. 5: does not apply to the pic17c42.
pic17c4x ds30412c-page 20 1996 microchip technology inc. bank 2 tmr1 10h xxxx xxxx uuuu uuuu uuuu uuuu tmr2 11h xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 12h xxxx xxxx uuuu uuuu uuuu uuuu tmr3h 13h xxxx xxxx uuuu uuuu uuuu uuuu pr1 14h xxxx xxxx uuuu uuuu uuuu uuuu pr2 15h xxxx xxxx uuuu uuuu uuuu uuuu pr3/ca1l 16h xxxx xxxx uuuu uuuu uuuu uuuu pr3/ca1h 17h xxxx xxxx uuuu uuuu uuuu uuuu bank 3 pw1dcl 10h xx-- ---- uu-- ---- uu-- ---- pw2dcl 11h xx-- ---- uu-- ---- uu-- ---- pw1dch 12h xxxx xxxx uuuu uuuu uuuu uuuu pw2dch 13h xxxx xxxx uuuu uuuu uuuu uuuu ca2l 14h xxxx xxxx uuuu uuuu uuuu uuuu ca2h 15h xxxx xxxx uuuu uuuu uuuu uuuu tcon1 16h 0000 0000 0000 0000 uuuu uuuu tcon2 17h 0000 0000 0000 0000 uuuu uuuu unbanked prodl (5) 18h xxxx xxxx uuuu uuuu uuuu uuuu prodh (5) 19h xxxx xxxx uuuu uuuu uuuu uuuu table 4-4: initialization conditions for special function registers (cont.d) register address power-on reset mclr reset wdt reset wake-up from sleep through interrupt legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. note 1: one or more bits in intsta, pir will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the glintd bit is cleared, the pc is loaded with the interrupt vector. 3: see table 4-3 for reset value of speci? condition. 4: only applies to the pic17c42. 5: does not apply to the pic17c42.
1996 microchip technology inc. ds30412c-page 21 pic17c4x 5.0 interrupts the pic17c4x devices have 11 sources of interrupt: external interrupt from the ra0/int pin change on rb7:rb0 pins tmr0 over?w tmr1 over?w tmr2 over?w tmr3 over?w usart transmit buffer empty usart receive buffer full capture1 capture2 t0cki edge occurred there are four registers used in the control and status of interrupts. these are: cpusta intsta pie pir the cpusta register contains the glintd bit. this is the global interrupt disable bit. when this bit is set, all interrupts are disabled. this bit is part of the controller core functionality and is described in the memory orga- nization section. when an interrupt is responded to, the glintd bit is automatically set to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with the interrupt vector address. there are four interrupt vectors. each vector address is for a speci? interrupt source (except the peripheral interrupts which have the same vector address). these sources are: external interrupt from the ra0/int pin tmr0 over?w t0cki edge occurred any peripheral interrupt when program execution vectors to one of these inter- rupt vector addresses (except for the peripheral inter- rupt address), the interrupt ?g bit is automatically cleared. vectoring to the peripheral interrupt vector address does not automatically clear the source of the interrupt. in the peripheral interrupt service routine, the source(s) of the interrupt can be determined by testing the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid in?ite interrupt requests. all of the individual interrupt ?g bits will be set regard- less of the status of their corresponding mask bit or the glintd bit. for external interrupt events, there will be an interrupt latency. for two cycle instructions, the latency could be one instruction cycle longer. the ?eturn from interrupt instruction, retfie , can be used to mark the end of the interrupt service routine. when this instruction is executed, the stack is ?oped? and the glintd bit is cleared (to re-enable interrupts). figure 5-1: interrupt logic tmr1if tmr1ie tmr2if tmr2ie tmr3if tmr3ie ca1if ca1ie ca2if ca2ie txif txie rcif rcie rbif rbie t0if t0ie intf inte t0ckif t0ckie glintd peie wake-up (if in sleep mode) or terminate long write interrupt to cpu peif this document was created with framemake r404
pic17c4x ds30412c-page 22 1996 microchip technology inc. 5.1 interrupt status register (intst a) the interrupt status/control register (intsta) records the individual interrupt requests in ?g bits, and con- tains the individual interrupt enable bits (not for the peripherals). the peif bit is a read only, bit wise or of all the periph- eral ?g bits in the pir register (figure 5-4). care should be taken when clearing any of the intsta register enable bits when interrupts are enabled (glintd is clear). if any of the intsta ?g bits (t0if, intf, t0ckif, or peif) are set in the same instruction cycle as the corresponding interrupt enable bit is cleared, the device will vector to the reset address (0x00). when disabling any of the intsta enable bits, the glintd bit should be set (disabled). note: t0if, intf, t0ckif, or peif will be set by the speci?d condition, even if the corre- sponding interrupt enable bit is clear (inter- rupt disabled) or the glintd bit is set (all interrupts disabled). figure 5-2: intsta register (address: 07h, unbanked) r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 peif t0ckif t0if intf peie t0ckie t0ie inte r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: peif : peripheral interrupt flag bit this bit is the or of all peripheral interrupt ?g bits and?d with their corresponding enable bits. 1 = a peripheral interrupt is pending 0 = no peripheral interrupt is pending bit 6: t0ckif : external interrupt on t0cki pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h). 1 = the software speci?d edge occurred on the ra1/t0cki pin 0 = the software speci?d edge did not occur on the ra1/t0cki pin bit 5: t0if : tmr0 over?w interrupt flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h). 1 = tmr0 over?wed 0 = tmr0 did not over?w bit 4: intf : external interrupt on int pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h). 1 = the software speci?d edge occurred on the ra0/int pin 0 = the software speci?d edge did not occur on the ra0/int pin bit 3: peie : peripheral interrupt enable bit this bit enables all peripheral interrupts that have their corresponding enable bits set. 1 = enable peripheral interrupts 0 = disable peripheral interrupts bit 2: t0ckie : external interrupt on t0cki pin enable bit 1 = enable software speci?d edge interrupt on the ra1/t0cki pin 0 = disable interrupt on the ra1/t0cki pin bit 1: t0ie : tmr0 over?w interrupt enable bit 1 = enable tmr0 over?w interrupt 0 = disable tmr0 over?w interrupt bit 0: inte : external interrupt on ra0/int pin enable bit 1 = enable software speci?d edge interrupt on the ra0/int pin 0 = disable software speci?d edge interrupt on the ra0/int pin
1996 microchip technology inc. ds30412c-page 23 pic17c4x 5.2 p eripheral interrupt enab le register (pie) this register contains the individual ?g bits for the peripheral interrupts. figure 5-3: pie register (address: 17h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbie : portb interrupt on change enable bit 1 = enable portb interrupt on change 0 = disable portb interrupt on change bit 6: tmr3ie : timer3 interrupt enable bit 1 = enable timer3 interrupt 0 = disable timer3 interrupt bit 5: tmr2ie : timer2 interrupt enable bit 1 = enable timer2 interrupt 0 = disable timer2 interrupt bit 4: tmr1ie : timer1 interrupt enable bit 1 = enable timer1 interrupt 0 = disable timer1 interrupt bit 3: ca2ie : capture2 interrupt enable bit 1 = enable capture interrupt on rb1/cap2 pin 0 = disable capture interrupt on rb1/cap2 pin bit 2: ca1ie : capture1 interrupt enable bit 1 = enable capture interrupt on rb2/cap1 pin 0 = disable capture interrupt on rb2/cap1 pin bit 1: txie : usart transmit interrupt enable bit 1 = enable transmit buffer empty interrupt 0 = disable transmit buffer empty interrupt bit 0: rcie : usart receive interrupt enable bit 1 = enable receive buffer full interrupt 0 = disable receive buffer full interrupt
pic17c4x ds30412c-page 24 1996 microchip technology inc. 5.3 p eripheral interr upt request register (pir) this register contains the individual ?g bits for the peripheral interrupts. note: these bits will be set by the speci?d con- dition, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the glintd bit is set (all interrupts dis- abled). before enabling an interrupt, the user may wish to clear the interrupt ?g to ensure that the program does not immedi- ately branch to the peripheral interrupt ser- vice routine. figure 5-4: pir register (address: 16h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r - 1 r - 0 rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbif : portb interrupt on change flag bit 1 = one of the portb inputs changed (software must end the mismatch condition) 0 = none of the portb inputs have changed bit 6: tmr3if : timer3 interrupt flag bit if capture1 is enabled (ca1/pr 3 = 1) 1 = timer3 over?wed 0 = timer3 did not over?w if capture1 is disabled (ca1/pr 3 = 0) 1 = timer3 value has rolled over to 0000h from equalling the period register (pr3h:pr3l) value 0 = timer3 value has not rolled over to 0000h from equalling the period register (pr3h:pr3l) value bit 5: tmr2if : timer2 interrupt flag bit 1 = timer2 value has rolled over to 0000h from equalling the period register (pr2) value 0 = timer2 value has not rolled over to 0000h from equalling the period register (pr2) value bit 4: tmr1if : timer1 interrupt flag bit if timer1 is in 8-bit mode (t16 = 0) 1 = timer1 value has rolled over to 0000h from equalling the period register (pr) value 0 = timer1 value has not rolled over to 0000h from equalling the period register (pr2) value if timer1 is in 16-bit mode (t16 = 1) 1 = tmr1:tmr2 value has rolled over to 0000h from equalling the period register (pr1:pr2) value 0 = tmr1:tmr2 value has not rolled over to 0000h from equalling the period register (pr1:pr2) value bit 3: ca2if : capture2 interrupt flag bit 1 = capture event occurred on rb1/cap2 pin 0 = capture event did not occur on rb1/cap2 pin bit 2: ca1if : capture1 interrupt flag bit 1 = capture event occurred on rb0/cap1 pin 0 = capture event did not occur on rb0/cap1 pin bit 1: txif : usart transmit interrupt flag bit 1 = transmit buffer is empty 0 = transmit buffer is full bit 0: rcif : usart receive interrupt flag bit 1 = receive buffer is full 0 = receive buffer is empty
1996 microchip technology inc. ds30412c-page 25 pic17c4x 5.4 interrupt operation global interrupt disable bit, glintd (cpusta<4>), enables all unmasked interrupts (if clear) or disables all interrupts (if set). individual interrupts can be disabled through their corresponding enable bits in the intsta register. peripheral interrupts need either the global peripheral enable peie bit disabled, or the speci? peripheral enable bit disabled. disabling the peripher- als via the global peripheral enable bit, disables all peripheral interrupts. glintd is set on reset (interrupts disabled). the retfie instruction allows returning from interrupt and re-enable interrupts at the same time. when an interrupt is responded to, the glintd bit is automatically set to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with interrupt vector. there are four interrupt vectors to reduce interrupt latency. the peripheral interrupt vector has multiple interrupt sources. once in the peripheral interrupt service rou- tine, the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the peripheral interrupt ?g bit(s) must be cleared in software before re- enabling interrupts to avoid continuous interrupts. the pic17c4x devices have four interrupt vectors. these vectors and their hardware priority are shown in table 5-1. if two enabled interrupts occur ?t the same time? the interrupt of the highest priority will be ser- viced ?st. this means that the vector address of that interrupt will be loaded into the program counter (pc). table 5-1: interrupt vectors/ priorities address vector priority 0008h external interrupt on ra0/ int pin (intf) 1 (highest) 0010h tmr0 over?w interrupt (t0if) 2 0018h external interrupt on t0cki (t0ckif) 3 0020h peripherals (peif) 4 (lowest) note 1: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the glintd bit. note 2: when disabling any of the intsta enable bits, the glintd bit should be set (disabled). note 3: for the pic17c42 only: if an interrupt occurs while the global inter- rupt disable (glintd) bit is being set, the glintd bit may unintentionally be re- enabled by the users interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an interrupt occurs simultaneously with an instruction that sets the glintd bit. 2. the program branches to the interrupt vector and executes the interrupt ser- vice routine. 3. the interrupt service routine com- pletes with the execution of the ret- fie instruction. this causes the glintd bit to be cleared (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts. the method to ensure that interrupts are globally disabled is: 1. ensure that the glintd bit was set by the instruction, as shown in the follow- ing code: loop bsf cpusta, glintd ; disable global ; interrupt btfss cpusta, glintd ; global interrupt ; disabled? goto loop ; no, try again ; yes, continue ; with program ; low
pic17c4x ds30412c-page 26 1996 microchip technology inc. 5.5 ra0/ int interrupt the external interrupt on the ra0/int pin is edge trig- gered. either the rising edge, if intedg bit (t0sta<7>) is set, or the falling edge, if intedg bit is clear. when a valid edge appears on the ra0/int pin, the intf bit (intsta<4>) is set. this interrupt can be disabled by clearing the inte control bit (intsta<0>). the int interrupt can wake the processor from sleep. see section 14.4 for details on sleep operation. 5.6 tmr0 interrupt an over?w (ffffh 0000h) in tmr0 will set the t0if (intsta<5>) bit. the interrupt can be enabled/ disabled by setting/clearing the t0ie control bit (intsta<1>). for operation of the timer0 module, see section 11.0. 5.7 t0ck i interrupt the external interrupt on the ra1/t0cki pin is edge triggered. either the rising edge, if the t0se bit (t0sta<6>) is set, or the falling edge, if the t0se bit is clear. when a valid edge appears on the ra1/t0cki pin, the t0ckif bit (intsta<6>) is set. this interrupt can be disabled by clearing the t0ckie control bit (intsta<2>). the t0cki interrupt can wake up the processor from sleep. see section 14.4 for details on sleep operation. 5.8 p er ipheral interrupt the peripheral interrupt ?g indicates that at least one of the peripheral interrupts occurred (peif is set). the peif bit is a read only bit, and is a bit wise or of all the ?g bits in the pir register and?d with the corre- sponding enable bits in the pie register. some of the peripheral interrupts can wake the processor from sleep. see section 14.4 for details on sleep opera- tion. figure 5-5: int pin / t0cki pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 osc2 ra0/int or ra1/t0cki intf or t0ckif glintd pc instruction executed system bus instruction fetched pc pc + 1 addr (vector) pc inst (pc) inst (pc+1) inst (pc) dummy dummy yy yy + 1 retfie retfie inst (pc+1) inst (vector) addr addr addr addr addr inst (yy + 1) dummy pc + 1
1996 microchip technology inc. ds30412c-page 27 pic17c4x 5.9 conte xt sa ving during interrupts during an interrupt, only the returned pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt; e.g. wreg, alusta and the bsr registers. this requires implementation in soft- ware. example 5-1 shows the saving and restoring of infor- mation for an interrupt service routine. the push and pop routines could either be in each interrupt service routine or could be subroutines that were called. depending on the application, other registers may also need to be saved, such as pclath. example 5-1: saving status and wreg in ram ; ; the addresses that are used to store the cpusta and wreg values ; must be in the data memory address range of 18h - 1fh. up to ; 8 locations can be saved and restored using ; the movfp instruction. this instruction neither affects the status ; bits, nor corrupts the wreg register. ; ; push movfp wreg, temp_w ; save wreg movfp alusta, temp_status ; save alusta movfp bsr, temp_bsr ; save bsr isr : ; this is the interrupt service routine : pop movfp temp_w, wreg ; restore wreg movfp temp_status, alusta ; restore alusta movfp temp_bsr, bsr ; restore bsr retfie ; return from interrupts enabled
pic17c4x ds30412c-page 28 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 29 pic17c4x 6.0 memory organization there are two memory blocks in the pic17c4x; pro- gram memory and data memory. each block has its own bus, so that access to each block can occur during the same oscillator cycle. the data memory can further be broken down into gen- eral purpose ram and the special function registers (sfrs). the operation of the sfrs that control the ?ore are described here. the sfrs used to control the peripheral modules are described in the section dis- cussing each individual peripheral module. 6.1 pr ogram memor y or ganization pic17c4x devices have a 16-bit program counter capable of addressing a 64k x 16 program memory space. the reset vector is at 0000h and the interrupt vectors are at 0008h, 0010h, 0018h, and 0020h (figure 6-1). 6.1.1 program memory operation the pic17c4x can operate in one of four possible pro- gram memory con?urations. the con?uration is selected by two con?uration bits. the possible modes are: microprocessor microcontroller extended microcontroller protected microcontroller the microcontroller and protected microcontroller modes only allow internal execution. any access beyond the program memory reads unknown data. the protected microcontroller mode also enables the code protection feature. the extended microcontroller mode accesses both the internal program memory as well as external program memory. execution automatically switches between internal and external memory. the 16-bits of address allow a program memory range of 64k-words. the microprocessor mode only accesses the external program memory. the on-chip program memory is ignored. the 16-bits of address allow a program mem- ory range of 64k-words. microprocessor mode is the default mode of an unprogrammed device. the different modes allow different access to the con- ?uration bits, test memory, and boot rom. table 6-1 lists which modes can access which areas in memory. test memory and boot memory are not required for normal operation of the device. care should be taken to ensure that no unintended branches occur to these areas. figure 6-1: program memory map and stack pc<15:0> stack level 1 stack level 16 reset vector int pin interrupt vector timer0 interrupt vector t0cki pin interrupt vector peripheral interrupt vector fosc0 fosc1 wdtps0 wdtps1 pm0 reserved pm1 reserved con?uration memory space user memory space (1) call, return retfie, retlw 16 0000h 0008h 0010h 0020h 0021h 0018h 7ffh fdffh fe00h fe01h fe02h fe03h fe04h fe05h fe06h fe07h fe0fh test eprom boot rom fe10h ff5fh ff60h ffffh fffh 1fffh (pic17c42, (pic17c43 (pic17c44) reserved pm2 (2) fe08h pic17cr42, pic17c42a) pic17cr43) note 1: user memory space may be internal, external, or both. the memory con?uration depends on the processor mode. 2: this location is reserved on the pic17c42. fe0eh this document was created with framemake r404
pic17c4x ds30412c-page 30 1996 microchip technology inc. table 6-1: mode memory access operating mode internal program memory con?uration bits, test memory, boot rom microprocessor no access no access microcontroller access access extended microcontroller access no access protected microcontroller access access the pic17c4x can operate in modes where the pro- gram memory is off-chip. they are the microprocessor and extended microcontroller modes. the micropro- cessor mode is the default for an unprogrammed device. regardless of the processor mode, data memory is always on-chip. figure 6-2: memory map in different modes microprocessor mode 0000h ffffh external program memory external program memory 0800h ffffh 0000h 07ffh on-chip program memory extended microcontroller mode microcontroller modes 0000h 07ffh 0800h fe00h ffffh off-chip on-chip off-chip on-chip off-chip on-chip 00h ffh 00h ffh 00h ffh off-chip on-chip off-chip on-chip off-chip on-chip program space data space con?. bits test memory boot rom pic17c42, 0000h ffffh external program memory external program memory 1000h/ ffffh 0000h 0000h 0fffh/1fffh 1000h/2000h fe00h ffffh off-chip on-chip off-chip on-chip off-chip on-chip con?. bits test memory boot rom program space data space 00h ffh 1ffh 120h off-chip on-chip 00h ffh 1ffh 120h off-chip on-chip 00h ffh 1ffh 120h off-chip on-chip 0fffh/1fffh 2000h pic17cr42, pic17c42a pic17c43, pic17cr43, pic17c44 on-chip program memory on-chip program memory on-chip program memory
1996 microchip technology inc. ds30412c-page 31 pic17c4x 6.1.2 external memory interface when either microprocessor or extended microcontrol- ler mode is selected, portc, portd and porte are con?ured as the system bus. portc and portd are the multiplexed address/data bus and porte is for the control signals. external components are needed to demultiplex the address and data. this can be done as shown in figure 6-4. the waveforms of address and data are shown in figure 6-3. for complete timings, please refer to the electrical speci?ation section. figure 6-3: external program memory access waveforms the system bus requires that there is no bus con?ct (minimal leakage), so the output value (address) will be capacitively held at the desired value. as the speed of the processor increases, external eprom memory with faster access time must be used. table 6-2 lists external memory speed requirements for a given pic17c4x device frequency. q3 q1 q2 q4 q3 q1 q2 q4 ad <15:0> ale oe wr '1' read cycle write cycle address out data in address out data out q1 in extended microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active. that is, they indicate the action that is occurring in the internal memory. the external memory access is ignored. this following selection is for use with microchip eproms. for interfacing to other manufacturers mem- ory, please refer to the electrical speci?ations of the desired pic17c4x device, as well as the desired mem- ory device to ensure compatibility. table 6-2: eprom memory access time ordering suffix pic17c4x oscillator frequency instruction cycle time (t cy ) eprom suf? pic17c42 pic17c43 pic17c44 8 mhz 500 ns -25 -25 16 mhz 250 ns -12 -15 20 mhz 200 ns -90 -10 25 mhz 160 ns n.a. -70 33 mhz 121 ns n.a. (1) note 1: the access times for this requires the use of fast srams. note: the external memory interface is not sup- ported for the lc devices. figure 6-4: typical external program memory connection diagram ad7-ad0 pic17c4x ad15-ad8 ale i/o (1) ad15-ad0 373 memory (msb) ax-a0 d7-d0 a15-a0 memory (lsb) ax-a0 d7-d0 373 138 (1) oe wr oe oe wr wr ce ce (2) (2) note 1: use of i/o pins is only required for paged memory. 2: this signal is unused for rom and eprom devices.
pic17c4x ds30412c-page 32 1996 microchip technology inc. 6.2 data memor y or ganization data memory is partitioned into two areas. the ?st is the general purpose registers (gpr) area, while the second is the special function registers (sfr) area. the sfrs control the operation of the device. portions of data memory are banked, this is for both areas. the gpr area is banked to allow greater than 232 bytes of general purpose ram. sfrs are for the registers that control the peripheral functions. banking requires the use of control bits for bank selection. these control bits are located in the bank select reg- ister (bsr). if an access is made to a location outside this banked region, the bsr bits are ignored. figure 6-5 shows the data memory map organization for the pic17c42 and figure 6-6 for all of the other pic17c4x devices. instructions movpf and movfp provide the means to move values from the peripheral area (?? to any loca- tion in the register file (??, and vice-versa. the de?i- tion of the ? range is from 0h to 1fh, while the ? range is 0h to ffh. the ? range has six more loca- tions than peripheral registers (eight locations for the pic17c42 device) which can be used as general pur- pose registers. this can be useful in some applications where variables need to be copied to other locations in the general purpose ram (such as saving status infor- mation during an interrupt). the entire data memory can be accessed either directly or indirectly through ?e select registers fsr0 and fsr1 (section 6.4). indirect addressing uses the appropriate control bits of the bsr for accesses into the banked areas of data memory. the bsr is explained in greater detail in section 6.8. 6.2.1 general purpose register (gpr) all devices have some amount of gpr area. the gprs are 8-bits wide. when the gpr area is greater than 232, it must be banked to allow access to the additional memory space. only the pic17c43 and pic17c44 devices have banked memory in the gpr area. to facilitate switching between these banks, the movlr bank instruction has been added to the instruction set. gprs are not initial- ized by a power-on reset and are unchanged on all other resets. 6.2.2 special function registers (sfr) the sfrs are used by the cpu and peripheral func- tions to control the operation of the device (figure 6-5 and figure 6-6). these registers are static ram. the sfrs can be classi?d into two sets, those associ- ated with the ?ore function and those related to the peripheral functions. those registers related to the ?ore are described here, while those related to a peripheral feature are described in the section for each peripheral feature. the peripheral registers are in the banked portion of memory, while the core registers are in the unbanked region. to facilitate switching between the peripheral banks, the movlb bank instruction has been provided.
1996 microchip technology inc. ds30412c-page 33 pic17c4x figure 6-5: pic17c42 register file map addr unbanked 00h indf0 01h fsr0 02h pcl 03h pclath 04h alusta 05h t0sta 06h cpusta 07h intsta 08h indf1 09h fsr1 0ah wreg 0bh tmr0l 0ch tmr0h 0dh tblptrl 0eh tblptrh 0fh bsr bank 0 bank 1 (1) bank 2 (1) bank 3 (1) 10h porta ddrc tmr1 pw1dcl 11h ddrb portc tmr2 pw2dcl 12h portb ddrd tmr3l pw1dch 13h rcsta portd tmr3h pw2dch 14h rcreg ddre pr1 ca2l 15h txsta porte pr2 ca2h 16h txreg pir pr3l/ca1l tcon1 17h spbrg pie pr3h/ca1h tcon2 18h 1fh general purpose ram 20h ffh note 1: sfr ?e locations 10h - 17h are banked. all other sfrs ignore the bank select register (bsr) bits. figure 6-6: pic17cr42/42a/43/r43/44 register file map addr unbanked 00h indf0 01h fsr0 02h pcl 03h pclath 04h alusta 05h t0sta 06h cpusta 07h intsta 08h indf1 09h fsr1 0ah wreg 0bh tmr0l 0ch tmr0h 0dh tblptrl 0eh tblptrh 0fh bsr bank 0 bank 1 (1) bank 2 (1) bank 3 (1) 10h porta ddrc tmr1 pw1dcl 11h ddrb portc tmr2 pw2dcl 12h portb ddrd tmr3l pw1dch 13h rcsta portd tmr3h pw2dch 14h rcreg ddre pr1 ca2l 15h txsta porte pr2 ca2h 16h txreg pir pr3l/ca1l tcon1 17h spbrg pie pr3h/ca1h tcon2 18h prodl 19h prodh 1ah 1fh general purpose ram (2) 20h ffh general purpose ram (2) note 1: sfr ?e locations 10h - 17h are banked. all other sfrs ignore the bank select register (bsr) bits. 2: general purpose registers (gpr) locations 20h - ffh and 120h - 1ffh are banked. all other gprs ignore the bank select register (bsr) bits.
pic17c4x ds30412c-page 34 1996 microchip technology inc. table 6-3: special function registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (3) unbanked 00h indf0 uses contents of fsr0 to address data memory (not a physical register) ---- ---- ---- ---- 01h fsr0 indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 02h pcl low order 8-bits of pc 0000 0000 0000 0000 03h (1) pclath holding register for upper 8-bits of pc 0000 0000 uuuu uuuu 04h alusta fs3 fs2 fs1 fs0 ov z dc c 1111 xxxx 1111 uuuu 05h t0sta intedg t0se t0cs ps3 ps2 ps1 ps0 0000 000- 0000 000- 06h (2) cpusta stkav glintd t o pd --11 11-- --11 qq-- 07h intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 08h indf1 uses contents of fsr1 to address data memory (not a physical register) ---- ---- ---- ---- 09h fsr1 indirect data memory address pointer 1 xxxx xxxx uuuu uuuu 0ah wreg working register xxxx xxxx uuuu uuuu 0bh tmr0l tmr0 register; low byte xxxx xxxx uuuu uuuu 0ch tmr0h tmr0 register; high byte xxxx xxxx uuuu uuuu 0dh tblptrl low byte of program memory table pointer (4) (4) 0eh tblptrh high byte of program memory table pointer (4) (4) 0fh bsr bank select register 0000 0000 0000 0000 bank 0 10h porta rbpu ra5 ra4 ra3 ra2 ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 11h ddrb data direction register for portb 1111 1111 1111 1111 12h portb portb data latch xxxx xxxx uuuu uuuu 13h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h rcreg serial port receive register xxxx xxxx uuuu uuuu 15h txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 16h txreg serial port transmit register xxxx xxxx uuuu uuuu 17h spbrg baud rate generator register xxxx xxxx uuuu uuuu bank 1 10h ddrc data direction register for portc 1111 1111 1111 1111 11h portc rc7/ ad7 rc6/ ad6 rc5/ ad5 rc4/ ad4 rc3/ ad3 rc2/ ad2 rc1/ ad1 rc0/ ad0 xxxx xxxx uuuu uuuu 12h ddrd data direction register for portd 1111 1111 1111 1111 13h portd rd7/ ad15 rd6/ ad14 rd5/ ad13 rd4/ ad12 rd3/ ad11 rd2/ ad10 rd1/ ad9 rd0/ ad8 xxxx xxxx uuuu uuuu 14h ddre data direction register for porte ---- -111 ---- -111 15h porte re2/wr re1/oe re0/ale ---- -xxx ---- -uuu 16h pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. shaded cells are unimplemented, read as '0'. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<15:8> whose contents are updated from or transferred to the upper byte of the program counter. 2: the t o and pd status bits in cpusta are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 4: the following values are for both tblptrl and tblptrh: all pic17c4x devices (power-on reset 0000 0000) and (all other resets 0000 0000) except the pic17c42 (power-on reset xxxx xxxx) and (all other resets uuuu uuuu) 5: the prodl and prodh registers are not implemented on the pic17c42.
1996 microchip technology inc. ds30412c-page 35 pic17c4x bank 2 10h tmr1 timer1 xxxx xxxx uuuu uuuu 11h tmr2 timer2 xxxx xxxx uuuu uuuu 12h tmr3l tmr3 register; low byte xxxx xxxx uuuu uuuu 13h tmr3h tmr3 register; high byte xxxx xxxx uuuu uuuu 14h pr1 timer1 period register xxxx xxxx uuuu uuuu 15h pr2 timer2 period register xxxx xxxx uuuu uuuu 16h pr3l/ca1l timer3 period register, low byte/capture1 register; low byte xxxx xxxx uuuu uuuu 17h pr3h/ca1h timer3 period register, high byte/capture1 register; high byte xxxx xxxx uuuu uuuu bank 3 10h pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 12h pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 14h ca2l capture2 low byte xxxx xxxx uuuu uuuu 15h ca2h capture2 high byte xxxx xxxx uuuu uuuu 16h tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 unbanked 18h (5) prodl low byte of 16-bit product (8 x 8 hardware multiply) xxxx xxxx uuuu uuuu 19h (5) prodh high byte of 16-bit product (8 x 8 hardware multiply) xxxx xxxx uuuu uuuu table 6-3: special function registers (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. shaded cells are unimplemented, read as '0'. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<15:8> whose contents are updated from or transferred to the upper byte of the program counter. 2: the t o and pd status bits in cpusta are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 4: the following values are for both tblptrl and tblptrh: all pic17c4x devices (power-on reset 0000 0000) and (all other resets 0000 0000) except the pic17c42 (power-on reset xxxx xxxx) and (all other resets uuuu uuuu) 5: the prodl and prodh registers are not implemented on the pic17c42.
pic17c4x ds30412c-page 36 1996 microchip technology inc. 6.2.2.1 alu status register (alusta) the alusta register contains the status bits of the arithmetic and logic unit and the mode control bits for the indirect addressing register. as with all the other registers, the alusta register can be the destination for any instruction. if the alusta register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the alusta register as destination may be different than intended. for example, clrf alusta will clear the upper four bits and set the z bit. this leaves the alusta register as 0000u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf , swapf and movwf instructions be used to alter the alusta register because these instructions do not affect any status bit. to see how other instructions affect the sta- tus bits, see the ?nstruction set summary. arithmetic and logic unit (alu) is capable of carrying out arithmetic or logical operations on two operands or a single operand. all single operand instructions oper- ate either on the wreg register or a ?e register. for two operand instructions, one of the operands is the wreg register and the other one is either a ?e register or an 8-bit immediate constant. note 1: the c and dc bits operate as a b orro w out bit in subtraction. see the sublw and subwf instructions for examples. note 2: the over?w bit will be set if the 2s com- plement result exceeds +127 or is less than -128. figure 6-7: alusta register (address: 04h, unbanked) r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - x r/w - x r/w - x r/w - x fs3 fs2 fs1 fs0 ov z dc c r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7-6: fs3:fs2 : fsr1 mode select bits 00 = post auto-decrement fsr1 value 01 = post auto-increment fsr1 value 1x = fsr1 value does not change bit 5-4: fs1:fs0 : fsr0 mode select bits 00 = post auto-decrement fsr0 value 01 = post auto-increment fsr0 value 1x = fsr0 value does not change bit 3: ov : over?w bit this bit is used for signed arithmetic (2s complement). it indicates an over?w of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = over?w occurred for signed arithmetic, (in this arithmetic operation) 0 = no over?w occurred bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the results of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow the polarity is reversed. bit 0: c : carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the most signi?ant bit of the result occurred note that a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrcf , rlcf ) instructions, this bit is loaded with either the high or low order bit of the source register. 0 = no carry-out from the most signi?ant bit of the result note: for borrow the polarity is reversed.
1996 microchip technology inc. ds30412c-page 37 pic17c4x 6.2.2.2 cpu status register (cpusta) the cpusta register contains the status and control bits for the cpu. this register is used to globally enable/disable interrupts. if only a speci? interrupt is desired to be enabled/disabled, please refer to the interrupt status (intsta) register and the peripheral interrupt enable (pie) register. this register also indi- cates if the stack is available and contains the power-down (pd ) and time-out (t o ) bits. the t o , pd , and stkav bits are not writable. these bits are set and cleared according to device logic. therefore, the result of an instruction with the cpusta register as destina- tion may be different than intended. figure 6-8: cpusta register (address: 06h, unbanked) u - 0 u - 0 r - 1 r/w - 1 r - 1 r - 1 u - 0 u - 0 stkav glintd t o pd r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5: stkav : stack available bit this bit indicates that the 4-bit stack pointer value is fh, or has rolled over from fh 0h (stack over?w). 1 = stack is available 0 = stack is full, or a stack over?w may have occurred (once this bit has been cleared by a stack over?w, only a device reset will set this bit) bit 4: glintd : global interrupt disable bit this bit disables all interrupts. when enabling interrupts, only the sources with their enable bits set can cause an interrupt. 1 = disable all interrupts 0 = enables all un-masked interrupts bit 3: t o : wdt time-out status bit 1 = after power-up or by a clrwdt instruction 0 = a watchdog timer time-out occurred bit 2: pd : power-down status bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1-0: unimplemented : read as '0'
pic17c4x ds30412c-page 38 1996 microchip technology inc. 6.2.2.3 tmr0 status/control register (t0sta) this register contains various control bits. bit7 (intedg) is used to control the edge upon which a sig- nal on the ra0/int pin will set the rb0/int interrupt ?g. the other bits con?ure the timer0 prescaler and clock source. (figure 11-1). figure 6-9: t0sta register (address: 05h, unbanked) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 intedg t0se t0cs ps3 ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented, reads as ? -n = value at por reset bit7 bit0 bit 7: intedg : ra0/int pin interrupt edge select bit this bit selects the edge upon which the interrupt is detected. 1 = rising edge of ra0/int pin generates interrupt 0 = falling edge of ra0/int pin generates interrupt bit 6: t0se : timer0 clock input edge select bit this bit selects the edge upon which tmr0 will increment. when t0cs = 0 1 = rising edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt 0 = falling edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt when t0cs = 1 don? care bit 5: t0cs : timer0 clock source select bit this bit selects the clock source for timer0. 1 = internal instruction clock cycle (t cy ) 0 = t0cki pin bit 4-1: ps3:ps0 : timer0 prescale selection bits these bits select the prescale value for timer0. bit 0: unimplemented : read as '0' ps3:ps0 prescale value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
1996 microchip technology inc. ds30412c-page 39 pic17c4x 6.3 stac k operation the pic17c4x devices have a 16 x 16-bit wide hard- ware stack (figure 6-1). the stack is not part of either the program or data memory space, and the stack pointer is neither readable nor writable. the pc is ?ushed onto the stack when a call instruction is executed or an interrupt is acknowledged. the stack is ?oped in the event of a return , retlw , or a retfie instruction execution. pclath is not affected by a ?ush or a ?op operation. the stack operates as a circular buffer, with the stack pointer initialized to '0' after all resets. there is a stack available bit (stkav) to allow software to ensure that the stack has not over?wed. the stkav bit is set after a device reset. when the stack pointer equals fh, stkav is cleared. when the stack pointer rolls over from fh to 0h, the stkav bit will be held clear until a device reset. after the device is ?ushed sixteen times (without a ?op?, the seventeenth push overwrites the value from the ?st push. the eighteenth push overwrites the second push (and so on). note 1: there is not a status bit for stack under- ?w. the stkav bit can be used to detect the under?w which results in the stack pointer being at the top of stack. note 2: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call , return , retlw , and retfie instruc- tions, or the vectoring to an interrupt vec- tor. note 3: after a reset, if a ?op operation occurs before a ?ush operation, the stkav bit will be cleared. this will appear as if the stack is full (under?w has occurred). if a ?ush operation occurs next (before another ?op?, the stkav bit will be locked clear. only a device reset will cause this bit to set. 6.4 indirect ad dressing indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not ?ed. that is, the register that is to be read or written can be modi?d by the program. this can be useful for data tables in the data memory. figure 6-10 shows the operation of indirect address- ing. this shows the moving of the value to the data memory address speci?d by the value of the fsr register. example 6-1 shows the use of indirect addressing to clear ram in a minimum number of instructions. a similar concept could be used to move a de?ed num- ber of bytes (block) of data to the usart transmit reg- ister (txreg). the starting address of the block of data to be transmitted could easily be modi?d by the program. figure 6-10: indirect addressing opcode address file = indfx fsr instruction executed instruction fetched ram opcode file
pic17c4x ds30412c-page 40 1996 microchip technology inc. 6.4.1 indirect addressing registers the pic17c4x has four registers for indirect address- ing. these registers are: indf0 and fsr0 indf1 and fsr1 registers indf0 and indf1 are not physically imple- mented. reading or writing to these registers activates indirect addressing, with the value in the correspond- ing fsr register being the address of the data. the fsr is an 8-bit register and allows addressing any- where in the 256-byte data memory address range. for banked memory, the bank of memory accessed is speci?d by the value in the bsr. if ?e indf0 (or indf1) itself is read indirectly via an fsr, all '0's are read (zero bit is set). similarly, if indf0 (or indf1) is written to indirectly, the operation will be equivalent to a nop, and the status bits are not affected. 6.4.2 indirect addressing operation the indirect addressing capability has been enhanced over that of the pic16cxx family. there are two con- trol bits associated with each fsr register. these two bits con?ure the fsr register to: auto-decrement the value (address) in the fsr after an indirect access auto-increment the value (address) in the fsr after an indirect access no change to the value (address) in the fsr after an indirect access these control bits are located in the alusta register. the fsr1 register is controlled by the fs3:fs2 bits and fsr0 is controlled by the fs1:fs0 bits. when using the auto-increment or auto-decrement features, the effect on the fsr is not re?cted in the alusta register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. if the fsr register contains a value of 0h, an indirect read will read 0h (zero bit is set) while an indirect write will be equivalent to a nop (status bits are not affected). indirect addressing allows single cycle data transfers within the entire data space. this is possible with the use of the movpf and movfp instructions, where either 'p' or 'f' is speci?d as indf0 (or indf1). if the source or destination of the indirect address is in banked memory, the location accessed will be deter- mined by the value in the bsr. a simple program to clear ram from 20h - ffh is shown in example 6-1. example 6-1: indirect addressing movlw 0x20 ; movwf fsr0 ; fsr0 = 20h bcf alusta, fs1 ; increment fsr bsf alusta, fs0 ; after access bcf alusta, c ; c = 0 movlw end_ram + 1 ; lp clrf indf0 ; addr(fsr) = 0 cpfseq fsr0 ; fsr0 = end_ram+1? goto lp ; no, clear next : ; yes, all ram is : ; cleared 6.5 t ab le p ointer (tblptrl and tblptrh) file registers tblptrl and tblptrh form a 16-bit pointer to address the 64k program memory space. the table pointer is used by instructions tablwt and tablrd . the tablrd and the tablwt instructions allow trans- fer of data between program and data space. the table pointer serves as the 16-bit address of the data word within the program memory. for a more complete description of these registers and the operation of table reads and table writes, see section 7.0. 6.6 t ab le latc h (tbla th, tbla tl) the table latch (tblat) is a 16-bit register, with tblath and tblatl referring to the high and low bytes of the register. it is not mapped into data or pro- gram memory. the table latch is used as a temporary holding latch during data transfer between program and data memory (see descriptions of instructions tablrd , tablwt , tlrd and tlwt ). for a more complete description of these registers and the operation of table reads and table writes, see section 7.0.
1996 microchip technology inc. ds30412c-page 41 pic17c4x 6.7 pr ogram counter module the program counter (pc) is a 16-bit register. pcl, the low byte of the pc, is mapped in the data memory. pcl is readable and writable just as is any other register. pch is the high byte of the pc and is not directly addressable. since pch is not mapped in data or pro- gram memory, an 8-bit register pclath (pc high latch) is used as a holding latch for the high byte of the pc. pclath is mapped into data memory. the user can read or write pch through pclath. the 16-bit wide pc is incremented after each instruc- tion fetch during q1 unless: modi?d by goto , call , lcall , return , retlw , or retfie instruction modi?d by an interrupt response due to destination write to pcl by an instruction ?kips are equivalent to a forced nop cycle at the skipped address. figure 6-11 and figure 6-12 show the operation of the program counter for various situations. figure 6-11: program counter operation figure 6-12: program counter using the call and goto instructions internal data bus <8> pclath 8 8 8 pch pcl 8 15 0 7 5 4 0 12 8 7 0 87 last write to pclath pclath opcode 5 3 8 pch pcl 13 15 using figure 6-11, the operations of the pc and pclath for different instructions are as follows: a) lcall instr uctions : an 8-bit destination address is provided in the instruction (opcode). pclath is unchanged. pclath pch opcode<7:0> pcl b) read instr uctions on pcl : any instruction that reads pcl. pcl data bus alu or destination pch pclath c) wr ite instr uctions on pcl : any instruction that writes to pcl. 8-bit data data bus pcl pclath pch d) read-modify-wr ite instr uctions on pcl: any instruction that does a read-write-modify operation on pcl, such as addwf pcl . read: pcl data bus alu write: 8-bit result data bus pcl pclath pch e) return instr uction: pch pclath stack pc<15:0> using figure 6-12, the operation of the pc and pclath for goto and call instructions is a follows: call , goto instr uctions : a 13-bit destination address is provided in the instruction (opcode). opcode<12:0> pc <12:0> pc<15:13> pclath<7:5> opcode<12:8> pclath <4:0> the read-modify-write only affects the pcl with the result. pch is loaded with the value in the pclath. for example, addwf pcl will result in a jump within the current page. if pc = 03f0h, wreg = 30h and pclath = 03h before instruction, pc = 0320h after the instruction. to accomplish a true 16-bit computed jump, the user needs to compute the 16-bit destination address, write the high byte to pclath and then write the low value to pcl. the following pc related operations do not change pclath: a) lcall , retlw , and retfie instructions. b) interrupt vector is forced onto the pc. c) read-modify-write instructions on pcl (e.g. bsf pcl ).
pic17c4x ds30412c-page 42 1996 microchip technology inc. 6.8 b ank select register (bsr) the bsr is used to switch between banks in the data memory area (figure 6-13). in the pic17c42, pic17cr42, and pic17c42a only the lower nibble is implemented. while in the pic17c43, pic17cr43, and pic17c44 devices, the entire byte is implemented. the lower nibble is used to select the peripheral regis- ter bank. the upper nibble is used to select the general purpose memory bank. all the special function registers (sfrs) are mapped into the data memory space. in order to accommodate the large number of registers, a banking scheme has been used. a segment of the sfrs, from address 10h to address 17h, is banked. the lower nibble of the bank select register (bsr) selects the currently active ?eripheral bank. effort has been made to group the peripheral registers of related functionality in one bank. however, it will still be necessary to switch from bank to bank in order to address all peripherals related to a single task. to assist this, a movlb bank instruction is in the instruction set. for the pic17c43, pic17cr43, and pic17c44 devices, the need for a large general purpose memory space dictated a general purpose ram banking scheme. the upper nibble of the bsr selects the cur- rently active general purpose ram bank. to assist this, a movlr bank instruction has been provided in the instruction set. if the currently selected bank is not implemented (such as bank 13), any read will read all '0's. any write is com- pleted to the bit bucket and the alu status bits will be set/cleared as appropriate. note: registers in bank 15 in the special func- tion register area, are reserved for microchip use. reading of registers in this bank may cause random values to be read. figure 6-13: bsr operation (pic17c43/r43/44) 7430 10h 17h bsr 01 234 15 ?? 20h ffh ?? ?? (1) (2) bank 15 bank 4 bank 3 bank 2 bank 1 bank 0 01 2 bank 2 bank 1 bank 0 15 bank 15 sfr banks gpr banks address range note 1: only banks 0 through bank 3 are implemented. selection of an unimplemented bank is not recommended . bank 15 is reserved for microchip use, reading of registers in this bank may cause random values to be read. 2: only banks 0 and bank 1 are implemented. selection of an unimplemented bank is not recommended.
1996 microchip technology inc. ds30412c-page 43 pic17c4x 7.0 table reads and table writes the pic17c4x has four instructions that allow the pro- cessor to move data from the data memory space to the program memory space, and vice versa. since the program memory space is 16-bits wide and the data memory space is 8-bits wide, two operations are required to move 16-bit values to/from the data mem- ory. the tlwt t,f and tablwt t,i,f instructions are used to write data from the data memory space to the program memory space. the tlrd t,f and tablrd t,i,f instructions are used to write data from the pro- gram memory space to the data memory space. the program memory can be internal or external. for the program memory access to be external, the device needs to be operating in extended microcontroller or microprocessor mode. figure 7-1 through figure 7-4 show the operation of these four instructions. figure 7-1: tlwt instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tlwt 1,f tlwt 0,f 1 note 1: 8-bit value, from register 'f', loaded into the high or low byte in tablat (16-bit). figure 7-2: tablwt instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tablwt 1,i,f tablwt 0,i,f 1 prog-mem (tblptr) 2 note 1: 8-bit value, from register 'f', loaded into the high or low byte in tablat (16-bit). 2: 16-bit tablat value written to address program memory (tblptr). 3: if ? = 1, then tblptr = tblptr + 1, if ? = 0, then tblptr is unchanged. 3 3 this document was created with framemake r404
pic17c4x ds30412c-page 44 1996 microchip technology inc. figure 7-3: tlrd instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tlrd 1,f tlrd 0,f 1 note 1: 8-bit value, from tablat (16-bit) high or low byte, loaded into register 'f'. figure 7-4: tablrd instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tablrd 1,i,f tablrd 0,i,f 1 prog-mem (tblptr) 2 note 1: 8-bit value, from tablat (16-bit) high or low byte, loaded into register 'f'. 2: 16-bit value at program memory (tblptr) loaded into tablat register. 3: if ? = 1, then tblptr = tblptr + 1, if ? = 0, then tblptr is unchanged. 3 3
1996 microchip technology inc. ds30412c-page 45 pic17c4x 7.1 t ab le writes to in ternal memor y a table write operation to internal memory causes a long write operation. the long write is necessary for programming the internal eprom. instruction execu- tion is halted while in a long write cycle. the long write will be terminated by any enabled interrupt. to ensure that the eprom location has been well programmed, a minimum programming time is required (see speci? cation #d114 ). having only one interrupt enabled to terminate the long write ensures that no unintentional interrupts will prematurely terminate the long write. the sequence of events for programming an internal program memory location should be: 1. disable all interrupt sources, except the source to terminate eprom program write. 2. raise mclr /v pp pin to the programming volt- age. 3. clear the wdt. 4. do the table write. the interrupt will terminate the long write. 5. verify the memory location (table read). note: programming requirements must be met. see timing speci?ation in electrical spec- i?ations for the desired device. violating these speci?ations (including tempera- ture) may result in eprom locations that are not fully programmed and may lose their state over time. 7.1.1 terminating long writes an interrupt source or reset are the only events that terminate a long write operation. terminating the long write from an interrupt source requires that the inter- rupt enable and ?g bits are set. the glintd bit only enables the vectoring to the interrupt address. if the t0cki, ra0/int, or tmr0 interrupt source is used to terminate the long write; the interrupt ?g, of the highest priority enabled interrupt, will terminate the long write and automatically be cleared. if a peripheral interrupt source is used to terminate the long write, the interrupt enable and ?g bits must be set. the interrupt ?g will not be automatically cleared upon the vectoring to the interrupt vector address. if the glintd bit is cleared prior to the long write, when the long write is terminated, the program will branch to the interrupt vector. if the glintd bit is set prior to the long write, when the long write is terminated, the program will not vector to the interrupt address. note 1: if an interrupt is pending, the tablwt is aborted (an nop is executed). the highest priority pending interrupt, from the t0cki, ra0/int, or tmr0 sources that is enabled, has its ?g cleared. note 2: if the interrupt is not being used for the program write timing, the interrupt should be disabled. this will ensure that the interrupt is not lost, nor will it termi- nate the long write prematurely. table 7-1: interrupt - table write interaction interrupt source glintd enable bit flag bit action ra0/int, tmr0, t0cki 0 0 1 1 1 1 0 1 1 0 x 1 terminate long table write (to internal program memory), branch to interrupt vector (branch clears ?g bit). none none terminate table write, do not branch to interrupt vector (?g is automatically cleared). peripheral 0 0 1 1 1 1 0 1 1 0 x 1 terminate table write, branch to interrupt vector. none none terminate table write, do not branch to interrupt vector (?g is set).
pic17c4x ds30412c-page 46 1996 microchip technology inc. 7.2 t ab le writes to e xternal memor y table writes to external memory are always two-cycle instructions. the second cycle writes the data to the external memory location. the sequence of events for an external memory write are the same for an internal write. note: if an interrupt is pending or occurs during the tablwt , the two cycle table write completes. the ra0/int, tmr0, or t0cki interrupt ?g is automatically cleared or the pending peripheral interrupt is acknowledged. 7.2.2 table write code the ? operand of the tablwt instruction can specify that the value in the 16-bit tblptr register is auto- matically incremented for the next write. in example 7-1, the tblptr register is not automatically incremented. example 7-1: table write clrwdt ; clear wdt movlw high (tbl_addr) ; load the table movwf tblptrh ; address movlw low (tbl_addr) ; movwf tblptrl ; movlw high (data) ; load hi byte tlwt 1, wreg ; in tablatch movlw low (data) ; load lo byte tablwt 0,0,wreg ; in tablatch ; and write to ; program memory ; (ext. sram) figure 7-5: tablwt write timing (external memory) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr tablwt inst (pc+1) inst (pc-1) tablwt cycle1 tablwt cycle2 inst (pc+2) data write cycle '1' pc pc+1 tbl pc+2 data out inst (pc+1) note: if external write glintd = '1', enable bit = '1', '1' flag bit, do table write. the highest pending interrupt is cleared.
1996 microchip technology inc. ds30412c-page 47 pic17c4x figure 7-6: consecutive tablwt write timing (external memory) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr pc tablwt1 tablwt2 inst (pc+2) inst (pc-1) tablwt1 cycle1 tablwt1 cycle2 tablwt2 cycle1 tablwt2 cycle2 data write cycle data write cycle inst (pc+3) pc+1 tbl1 pc+2 tbl2 pc+3 data out 1 data out 2 inst (pc+2)
pic17c4x ds30412c-page 48 1996 microchip technology inc. 7.3 t ab le reads the table read allows the program memory to be read. this allows constant data to be stored in the program memory space, and retrieved into data memory when needed. example 7-2 reads the 16-bit value at pro- gram memory address tblptr. after the dummy byte has been read from the tablath, the tablath is loaded with the 16-bit data from program memory address tblptr + 1. the ?st read loads the data into the latch, and can be considered a dummy read (unknown data loaded into 'f'). indf0 should be con- ?ured for either auto-increment or auto-decrement. example 7-2: table read movlw high (tbl_addr) ; load the table movwf tblptrh ; address movlw low (tbl_addr) ; movwf tblptrl ; tablrd 0,0,dummy ; dummy read, ; updates tablatch tlrd 1, indf0 ; read hi byte ; of tablatch tablrd 0,1,indf0 ; read lo byte ; of tablatch and ; update tablatch figure 7-7: tablrd timing figure 7-8: tablrd timing (consecutive tablrd instructions) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr tablrd inst (pc+1) inst (pc+2) inst (pc-1) tablrd cycle1 tablrd cycle2 inst (pc+1) data read cycle pc pc+1 tbl data in pc+2 '1' q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed tablrd1 tablrd2 inst (pc+2) inst (pc+3) inst (pc+2) ale oe wr inst (pc-1) tablrd1 cycle1 tablrd1 cycle2 tablrd2 cycle1 tablrd2 cycle2 data read cycle data read cycle '1' pc pc+1 pc+2 pc+3 tbl1 data in 1 tbl2 data in 2
1996 microchip technology inc. ds30412c-page 49 pic17c4x 8.0 hardware multiplier all pic17c4x devices except the pic17c42, have an 8 x 8 hardware multiplier included in the alu of the device. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product register (prodh:prodl). the multiplier does not affect any ?gs in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 8-1 shows a performance comparison between the pic17c42 and all other pic17cxx devices, which have the single cycle hardware multiply. example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each arguments most signi?ant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 multiply routine movfp arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl example 8-2: 8 x 8 signed multiply routine movfp arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movfp arg2, wreg btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 table 8-1: performance comparison routine device program memory (words) cycles (max) time @ 25 mhz @ 33 mhz 8 x 8 unsigned pic17c42 13 69 11.04 m s n/a all other pic17cxx devices 1 1 160 ns 121 ns 8 x 8 signed pic17c42 n/a all other pic17cxx devices 6 6 960 ns 727 ns 16 x 16 unsigned pic17c42 21 242 38.72 m s n/a all other pic17cxx devices 24 24 3.84 m s 2.91 m s 16 x 16 signed pic17c42 52 254 40.64 m s n/a all other pic17cxx devices 36 36 5.76 m s 4.36 m s this document was created with framemake r404
pic17c4x ds30412c-page 50 1996 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in 4 registers res3:res0. equation 8-1: 16 x 16 unsigned multiplication algorithm res3:res0 = arg1h:arg1l * arg2h:arg2l = (arg1h * arg2h * 2 16 )+ (arg1h * arg2l * 2 8 )+ (arg1l * arg2h * 2 8 )+ (arg1l * arg2l) example 8-3: 16 x 16 multiply routine movfp arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movpf prodh, res1 ; movpf prodl, res0 ; ; movfp arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movpf prodh, res3 ; movpf prodl, res2 ; ; movfp arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movfp arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ;
1996 microchip technology inc. ds30412c-page 51 pic17c4x example 8-4 shows the sequence to do an 16 x 16 signed multiply. equation 8-2 shows the algorithm that used. the 32-bit result is stored in four registers res3:res0. to account for the sign bits of the argu- ments, each argument pairs most signi?ant bit (msb) is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm res3:res0 = arg1h:arg1l * arg2h:arg2l = (arg1h * arg2h * 2 16 )+ (arg1h * arg2l * 2 8 )+ (arg1l * arg2h * 2 8 )+ (arg1l * arg2l) + (-1 * arg2h<7> * arg1h:arg1l * 2 16 )+ (-1 * arg1h<7> * arg2h:arg2l * 2 16 ) example 8-4: 16 x 16 signed multiply routine movfp arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movpf prodh, res1 ; movpf prodl, res0 ; ; movfp arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movpf prodh, res3 ; movpf prodl, res2 ; ; movfp arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movfp arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? goto sign_arg1 ; no, check arg1 movfp arg1l, wreg ; subwf res2 ; movfp arg1h, wreg ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? goto cont_code ; no, done movfp arg2l, wreg ; subwf res2 ; movfp arg2h, wreg ; subwfb res3 ; cont_code :
pic17c4x ds30412c-page 52 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 53 pic17c4x 9.0 i/o ports the pic17c4x devices have five i/o ports, porta through porte. portb through porte have a corre- sponding data direction register (ddr), which is used to con?ure the port pins as inputs or outputs. these ?e ports are made up of 33 i/o pins. some of these ports pins are multiplexed with alternate functions. portc, portd, and porte are multiplexed with the system bus. these pins are con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, these pins are general purpose i/o. porta and portb are multiplexed with the peripheral features of the device. these peripheral features are: timer modules capture module pwm module usart/sci module external interrupt pin when some of these peripheral modules are turned on, the port pin will automatically con?ure to the alternate function. the modules that do this are: pwm module usart/sci module when a pin is automatically con?ured as an output by a peripheral module, the pins data direction (ddr) bit is unknown. after disabling the peripheral module, the user should re-initialize the ddr bit to the desired con- ?uration. the other peripheral modules (which require an input) must have their data direction bit con?ured appropri- ately. note: a pin that is a peripheral input, can be con- ?ured as an output (ddrx is cleared). the peripheral events will be determined by the action output on the port pin. 9.1 por t a register porta is a 6-bit wide latch. porta does not have a corresponding data direction register (ddr). reading porta reads the status of the pins. the ra1 pin is multiplexed with tmr0 clock input, and ra4 and ra5 are multiplexed with the usart func- tions. the control of ra4 and ra5 as outputs is auto- matically con?ured by the usart module. 9.1.1 using ra2, ra3 as outputs the ra2 and ra3 pins are open drain outputs. to use the ra2 or the ra3 pin(s) as output(s), simply write to the porta register the desired value. a '0' will cause the pin to drive low, while a '1' will cause the pin to ?at (hi-impedance). an external pull-up resistor should be used to pull the pin high. writes to porta will not affect the other pins. figure 9-1: ra0 and ra1 block diagram note: when using the ra2 or ra3 pin(s) as out- put(s), read-modify-write instructions (such as bcf , bsf , btg ) on porta are not rec- ommended. such operations read the port pins, do the desired operation, and then write this value to the data latch. this may inadvertently cause the ra2 or ra3 pins to switch from input to output (or vice-versa). it is recommended to use a shadow regis- ter for porta. do the bit operations on this shadow register and then move it to porta. note: i/o pins have protection diodes to v dd and v ss . data b u s rd_porta (q2) this document was created with framemake r404
pic17c4x ds30412c-page 54 1996 microchip technology inc. figure 9-2: ra2 and ra3 block diagram note: i/o pins have protection diodes to v ss . data bus wr_porta (q4) qd q ck rd_porta (q2) figure 9-3: ra4 and ra5 block diagram note: i/o pins have protection diodes to v dd and v ss . data bus rd_porta (q2) serial port output signals serial port input signal oe = spen,sync,txen, cren , sren for ra4 oe = spen (sync +sync,csrc ) for ra5 table 9-1: porta functions table 9-2: registers/bits associated with porta name bit0 buffer type function ra0/int bit0 st input or external interrupt input. ra1/t0cki bit1 st input or clock input to the tmr0 timer/counter, and/or an external interrupt input. ra2 bit2 st input/output. output is open drain type. ra3 bit3 st input/output. output is open drain type. ra4/rx/dt bit4 st input or usart asynchronous receive or usart synchronous data. ra5/tx/ck bit5 st input or usart asynchronous transmit or usart synchronous clock. rbpu bit7 control bit for portb weak pull-ups. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 10h, bank 0 porta rbpu ra5 ra4 ra3 ra2 ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 05h, unbanked t0sta intedg t0se t0cs ps3 ps2 ps1 ps0 0000 000- 0000 000- 13h, bank 0 rcsta spen rc9 sren cren ferr oerr rc9d 0000 -00x 0000 -00u 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. shaded cells are not used by porta. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
1996 microchip technology inc. ds30412c-page 55 pic17c4x 9.2 por tb and ddrb register s portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is ddrb. a '1' in ddrb con?ures the corresponding port pin as an input. a '0' in the ddrb register con?ures the corresponding port pin as an output. reading portb reads the status of the pins, whereas writing to it will write to the port latch. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (porta<7>) bit. the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are enabled on any reset. portb also has an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb0 pin con?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb0) are compared with the value in the portb data latch. the ?ismatch outputs of rb7:rb0 are or?d together to generate the portb interrupt flag rbif (pir<7>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt by: a) read-write portb (such as; movpf portb, portb ). this will end mismatch condition. b) then, clear the rbif bit. a mismatch condition will continue to set the rbif bit. reading then writing portb will end the mismatch condition, and allow the rbif bit to be cleared. this interrupt on mismatch feature, together with soft- ware con?urable pull-ups on this port, allows easy interface to a key pad and make it possible for wake-up on key-depression. for an example, refer to an552 in the embedded control handbook . the interrupt on change feature is recommended for wake-up on operations where portb is only used for the interrupt on change feature and key depression operation. figure 9-4: block diagram of rb<7:4> and rb<1:0> port pins note: i/o pins have protection diodes to v dd and v ss . data bus q d ck q d ck weak pull-up port input latch port data oe wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in
pic17c4x ds30412c-page 56 1996 microchip technology inc. figure 9-5: block diagram of rb3 and rb2 port pins note: i/o pins have protection diodes to v dd and vss. data bus q d ck q d ck r weak pull-up port input latch port data oe pwm_select pwm_output wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in
1996 microchip technology inc. ds30412c-page 57 pic17c4x example 9-1 shows the instruction sequence to initial- ize portb. the bank select register (bsr) must be selected to bank 0 for the port to be initialized. example 9-1: initializing portb movlb 0 ; select bank 0 clrf portb ; initialize portb by clearing ; output data latches movlw 0xcf ; value used to initialize ; data direction movwf ddrb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs table 9-3: portb functions table 9-4: registers/bits associated with portb name bit buffer type function rb0/cap1 bit0 st input/output or the rb0/cap1 input pin. software programmable weak pull- up and interrupt on change features. rb1/cap2 bit1 st input/output or the rb1/cap2 input pin. software programmable weak pull- up and interrupt on change features. rb2/pwm1 bit2 st input/output or the rb2/pwm1 output pin. software programmable weak pull-up and interrupt on change features. rb3/pwm2 bit3 st input/output or the rb3/pwm2 output pin. software programmable weak pull-up and interrupt on change features. rb4/tclk12 bit4 st input/output or the external clock input to timer1 and timer2. software pro- grammable weak pull-up and interrupt on change features. rb5/tclk3 bit5 st input/output or the external clock input to timer3. software programmable weak pull-up and interrupt on change features. rb6 bit6 st input/output pin. software programmable weak pull-up and interrupt on change features. rb7 bit7 st input/output pin. software programmable weak pull-up and interrupt on change features. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 12h, bank 0 portb portb data latch xxxx xxxx uuuu uuuu 11h, bank 0 ddrb data direction register for portb 1111 1111 1111 1111 10h, bank 0 porta rbpu ra5 ra4 ra3 ra2 ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on condition. shaded cells are not used by portb. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c4x ds30412c-page 58 1996 microchip technology inc. 9.3 por tc and ddrc register s portc is an 8-bit bi-directional port. the correspond- ing data direction register is ddrc. a '1' in ddrc con- ?ures the corresponding port pin as an input. a '0' in the ddrc register con?ures the corresponding port pin as an output. reading portc reads the status of the pins, whereas writing to it will write to the port latch. portc is multiplexed with the system bus. when operating as the system bus, portc is the low order byte of the address/data bus (ad7:ad0). the timing for the system bus is shown in the electrical characteris- tics section. note: this port is con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, this port is a gen- eral purpose i/o. example 9-2 shows the instruction sequence to initial- ize portc. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. example 9-2: initializing portc movlb 1 ; select bank 1 clrf portc ; initialize portc data ; latches before setting ; the data direction ; register movlw 0xcf ; value used to initialize ; data direction movwf ddrc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 9-6: block diagram of rc<7:0> port pins note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data to d_bus ir instruction read data bus rd_portc wr_portc rd_ddrc wr_ddrc ex_en data/addr_out drv_sys sys bus control
1996 microchip technology inc. ds30412c-page 59 pic17c4x table 9-5: portc functions table 9-6: registers/bits associated with portc name bit buffer type function rc0/ad0 bit0 ttl input/output or system bus address/data pin. rc1/ad1 bit1 ttl input/output or system bus address/data pin. rc2/ad2 bit2 ttl input/output or system bus address/data pin. rc3/ad3 bit3 ttl input/output or system bus address/data pin. rc4/ad4 bit4 ttl input/output or system bus address/data pin. rc5/ad5 bit5 ttl input/output or system bus address/data pin. rc6/ad6 bit6 ttl input/output or system bus address/data pin. rc7/ad7 bit7 ttl input/output or system bus address/data pin. legend: ttl = ttl input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 11h, bank 1 portc rc7/ ad7 rc6/ ad6 rc5/ ad5 rc4/ ad4 rc3/ ad3 rc2/ ad2 rc1/ ad1 rc0/ ad0 xxxx xxxx uuuu uuuu 10h, bank 1 ddrc data direction register for portc 1111 1111 1111 1111 legend: x = unknown, u = unchanged. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c4x ds30412c-page 60 1996 microchip technology inc. 9.4 por td and ddrd register s portd is an 8-bit bi-directional port. the correspond- ing data direction register is ddrd. a '1' in ddrd con- ?ures the corresponding port pin as an input. a '0' in the ddrc register con?ures the corresponding port pin as an output. reading portd reads the status of the pins, whereas writing to it will write to the port latch. portd is multiplexed with the system bus. when operating as the system bus, portd is the high order byte of the address/data bus (ad15:ad8). the timing for the system bus is shown in the electrical character- istics section. note: this port is con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, this port is a gen- eral purpose i/o. example 9-3 shows the instruction sequence to initial- ize portd. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. example 9-3: initializing portd movlb 1 ; select bank 1 clrf portd ; initialize portd data ; latches before setting ; the data direction ; register movlw 0xcf ; value used to initialize ; data direction movwf ddrd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs figure 9-7: portd block diagram (in i/o port mode) note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data to d_bus ir instruction read data bus rd_portd wr_portd rd_ddrd wr_ddrd ex_en data/addr_out drv_sys sys bus control
1996 microchip technology inc. ds30412c-page 61 pic17c4x table 9-7: portd functions table 9-8: registers/bits associated with portd name bit buffer type function rd0/ad8 bit0 ttl input/output or system bus address/data pin. rd1/ad9 bit1 ttl input/output or system bus address/data pin. rd2/ad10 bit2 ttl input/output or system bus address/data pin. rd3/ad11 bit3 ttl input/output or system bus address/data pin. rd4/ad12 bit4 ttl input/output or system bus address/data pin. rd5/ad13 bit5 ttl input/output or system bus address/data pin. rd6/ad14 bit6 ttl input/output or system bus address/data pin. rd7/ad15 bit7 ttl input/output or system bus address/data pin. legend: ttl = ttl input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 13h, bank 1 portd rd7/ ad15 rd6/ ad14 rd5/ ad13 rd4/ ad12 rd3/ ad11 rd2/ ad10 rd1/ ad9 rd0/ ad8 xxxx xxxx uuuu uuuu 12h, bank 1 ddrd data direction register for portd 1111 1111 1111 1111 legend: x = unknown, u = unchanged. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c4x ds30412c-page 62 1996 microchip technology inc. 9.4.1 porte and ddre register porte is a 3-bit bi-directional port. the corresponding data direction register is ddre. a '1' in ddre con?- ures the corresponding port pin as an input. a '0' in the ddre register con?ures the corresponding port pin as an output. reading porte reads the status of the pins, whereas writing to it will write to the port latch. porte is multiplexed with the system bus. when operating as the system bus, porte contains the con- trol signals for the address/data bus (ad15:ad0). these control signals are address latch enable (ale), output enable (oe ), and write (wr ). the control sig- nals oe and wr are active low signals. the timing for the system bus is shown in the electrical characteris- tics section. note: this port is con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, this port is a gen- eral purpose i/o. example 9-4 shows the instruction sequence to initial- ize porte. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. example 9-4: initializing porte movlb 1 ; select bank 1 clrf porte ; initialize porte data ; latches before setting ; the data direction ; register movlw 0x03 ; value used to initialize ; data direction movwf ddre ; set re<1:0> as inputs ; re<2> as outputs ; re<7:3> are always ; read as '0' figure 9-8: porte block diagram (in i/o port mode) note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data data bus rd_porte wr_porte rd_ddre wr_ddre ex_en cntl drv_sys sys bus control
1996 microchip technology inc. ds30412c-page 63 pic17c4x table 9-9: porte functions table 9-10: registers/bits associated with porte name bit buffer type function re0/ale bit0 ttl input/output or system bus address latch enable (ale) control pin. re1/oe bit1 ttl input/output or system bus output enable (oe ) control pin. re2/wr bit2 ttl input/output or system bus write (wr ) control pin. legend: ttl = ttl input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 15h, bank 1 porte re2/wr re1/oe re0/ale ---- -xxx ---- -uuu 14h, bank 1 ddre data direction register for porte ---- -111 ---- -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. note 1: other (non power-up) resets include: external reset through mcl r and the watchdog timer reset.
pic17c4x ds30412c-page 64 1996 microchip technology inc. 9.5 i/o pr ogramming considerations 9.5.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. for example, the bcf and bsf instructions read the register into the cpu, execute the bit operation, and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g. bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and re-written to the data latch of this particu- lar pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. how- ever, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading a port reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions ( bcf, bsf , btg , etc.) on a port, the value of the port pins is read, the desired operation is performed with this value, and the value is then written to the port latch. example 9-5 shows the effect of two sequential read-modify-write instructions on an i/o port. example 9-5: read modify write instructions on an i/o port ; initial port settings: portb<7:4> inputs ; portb<3:0> outputs ; portb<7:6> have pull-ups and are ; not connected to other circuitry ; ; port latch port pins ; ---------- --------- ; bcf portb, 7 01pp pppp 11pp pppp bcf portb, 6 10pp pppp 11pp pppp ; bcf ddrb, 7 10pp pppp 11pp pppp bcf ddrb, 6 10pp pppp 10pp pppp ; ; note that the user may have expected the ; pin values to be 00pp pppp. the 2nd bcf ; caused rb7 to be latched as the pin value ; (high). 9.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 9- 9). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before executing the instruction that reads the values on that i/o port. otherwise, the previous state of that pin may be read into the cpu rather than the ?ew state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. note: a pin actively outputting a low or high should not be driven from external devices in order to change the level on this pin (i.e. ?ired-or? ?ired-and?. the resulting high output currents may damage the device. figure 9-9: successive i/o operation note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25 t cy - t pd ) where t cy = instruction cycle. therefore, at higher clock frequencies, a write followed by a read may be problematic. t pd = propagation delay pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w
1996 microchip technology inc. ds30412c-page 65 pic17c4x 10.0 overview of timer resources the pic17c4x has four timer modules. each module can generate an interrupt to indicate that an event has occurred. these timers are called: timer0 - 16-bit timer with programmable 8-bit prescaler timer1 - 8-bit timer timer2 - 8-bit timer timer3 - 16-bit timer for enhanced time-base functionality, two input cap- tures and two pulse width modulation (pwm) outputs are possible. the pwms use the tmr1 and tmr2 resources and the input captures use the tmr3 resource. 10.1 timer0 over vie w the timer0 module is a simple 16-bit over?w counter. the clock source can be either the internal system clock (fosc/4) or an external clock. the timer0 module also has a programmable pres- caler option. the ps3:ps0 bits (t0sta<4:1>) deter- mine the prescaler value. tmr0 can increment at the following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, 1:256. when timer0s clock source is an external clock, the timer0 module can be selected to increment on either the rising or falling edge. synchronization of the external clock occurs after the prescaler. when the prescaler is used, the external clock frequency may be higher then the devices fre- quency. the maximum frequency is 50 mhz, given the high and low time requirements of the clock. 10.2 timer1 over vie w the timer0 module is an 8-bit timer/counter with an 8- bit period register (pr1). when the tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated when enabled. in counter mode, the clock comes from the rb4/tclk12 pin, which can also be selected to be the clock for the timer2 module. tmr1 can be concatenated to tmr2 to form a 16-bit timer. the tmr1 register is the lsb and tmr2 is the msb. when in the 16-bit timer mode, there is a corre- sponding 16-bit period register (pr2:pr1). when the tmr2:tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated when enabled. 10.3 timer2 over vie w the tmr2 module is an 8-bit timer/counter with an 8- bit period register (pr2). when the tmr2 value rolls over from the period match value to 0h, the tmr2if ?g is set, and an interrupt will be generated when enabled. in counter mode, the clock comes from the rb4/tclk12 pin, which can also be selected to be the clock for the tmr1 module. tmr1 can be concatenated to tmr2 to form a 16-bit timer. the tmr2 register is the msb and tmr1 is the lsb. when in the 16-bit timer mode, there is a corre- sponding 16-bit period register (pr2:pr1). when the tmr2:tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated when enabled. 10.4 timer3 o ver vie w the timer3 module is a 16-bit timer/counter with a 16- bit period register. when the tmr3h:tmr3l value rolls over to 0h, the tmr3if bit is set and an interrupt will be generated when enabled. in counter mode, the clock comes from the rb5/tclk3 pin. when operating in the dual capture mode, the period registers become the second 16-bit capture register. 10.5 role of the timer/counter s the timer modules are general purpose, but have ded- icated resources associated with them. timer1 and timer2 are the time-bases for the two pulse width modulation (pwm) outputs, while timer3 is the time- base for the two input captures. this document was created with framemake r404
pic17c4x ds30412c-page 66 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 67 pic17c4x 11.0 timer0 the timer0 module consists of a 16-bit timer/counter, tmr0. the high byte is tmr0h and the low byte is tmr0l. a software programmable 8-bit prescaler makes an effective 24-bit over?w timer. the clock source is also software programmable as either the internal instruction clock or the ra1/t0cki pin. the control bits for this module are in register t0sta (figure 11-1). figure 11-1: t0sta register (address: 05h, unbanked) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 intedg t0se t0cs ps3 ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented, read as '0' -n = value at por reset bit7 bit0 bit 7: intedg : ra0/int pin interrupt edge select bit this bit selects the edge upon which the interrupt is detected 1 = rising edge of ra0/int pin generates interrupt 0 = falling edge of ra0/int pin generates interrupt bit 6: t0se : timer0 clock input edge select bit this bit selects the edge upon which tmr0 will increment when t0cs = 0 1 = rising edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt 0 = falling edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt when t0cs = 1 don? care bit 5: t0cs : timer0 clock source select bit this bit selects the clock source for tmr0. 1 = internal instruction clock cycle (t cy ) 0 = t0cki pin bit 4-1: ps3:ps0 : timer0 prescale selection bits these bits select the prescale value for tmr0. bit 0: unimplemented : read as '0' ps3:ps0 prescale value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 this document was created with framemake r404
pic17c4x ds30412c-page 68 1996 microchip technology inc. 11.1 timer0 operation when the t0cs (t0sta<5>) bit is set, tmr0 incre- ments on the internal clock. when t0cs is clear, tmr0 increments on the external clock (ra1/t0cki pin). the external clock edge can be con?ured in software. when the t0se (t0sta<6>) bit is set, the timer will increment on the rising edge of the ra1/t0cki pin. when t0se is clear, the timer will increment on the fall- ing edge of the ra1/t0cki pin. the prescaler can be programmed to introduce a prescale of 1:1 to 1:256. the timer increments from 0000h to ffffh and rolls over to 0000h. on over?w, the tmr0 interrupt flag bit (t0if) is set. the tmr0 interrupt can be masked by clearing the corresponding tmr0 interrupt enable bit (t0ie). the tmr0 interrupt flag bit (t0if) is automati- cally cleared when vectoring to the tmr0 interrupt vec- tor. 11.2 using t imer0 with external cloc k when the external clock input is used for timer0, it is synchronized with the internal phase clocks. figure 11-3 shows the synchronization of the external clock. this synchronization is done after the prescaler. the output of the prescaler (psout) is sampled twice in every instruction cycle to detect a rising or a falling edge. the timing requirements for the external clock are detailed in the electrical speci?ation section for the desired device. 11.2.1 delay from external clock edge since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time tmr0 is actually incremented. figure 11-3 shows that this delay is between 3t osc and 7t osc . thus, for example, mea- suring the interval between two edges (e.g. period) will be accurate within 4t osc ( 121 ns @ 33 mhz). figure 11-2: timer0 module block diagram figure 11-3: tmr0 timing with external clock (increment on falling edge) ra1/t0cki synchronization prescaler (8 stage async ripple counter) t0se (t0sta<6>) fosc/4 t0cs (t0sta<5>) ps3:ps0 (t0sta<4:1>) q2 q4 0 1 tmr0h<8> tmr0l<8> interrupt on over?w sets t0if (intsta<5>) 4 psout q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 prescaler output (psout) sampled prescaler output increment tmr0 tmr0 t0 t0 + 1 t0 + 2 (note 3) (note 2) note 1: the delay from the t0cki edge to the tmr0 increment is 3tosc to 7tosc. 2: = psout is sampled here. 3: the psout high time is too short and is missed by the sampling circuit. (note 1)
1996 microchip technology inc. ds30412c-page 69 pic17c4x 11.3 read/write consideration f or tmr0 although tmr0 is a 16-bit timer/counter, only 8-bits at a time can be read or written during a single instruction cycle. care must be taken during any read or write. 11.3.1 reading 16-bit value the problem in reading the entire 16-bit value is that after reading the low (or high) byte, its value may change from ffh to 00h. example 11-1 shows a 16-bit read. to ensure a proper read, interrupts must be disabled during this routine. example 11-1: 16-bit read movpf tmr0l, tmplo ;read low tmr0 movpf tmr0h, tmphi ;read high tmr0 movfp tmplo, wreg ;tmplo -> wreg cpfslt tmr0l ;tmr0l < wreg? return ;no then return movpf tmr0l, tmplo ;read low tmr0 movpf tmr0h, tmphi ;read high tmr0 return ;return 11.3.2 writing a 16-bit value to tmr0 since writing to either tmr0l or tmr0h will effectively inhibit increment of that half of the tmr0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to tmr0l ?st and tmr0h next in two consecutive instructions, as shown in example 11-2. the interrupt must be disabled. any write to either tmr0l or tmr0h clears the prescaler. example 11-2: 16-bit write bsf cpusta, glintd ; disable interrupt movfp ram_l, tmr0l ; movfp ram_h, tmr0h ; bcf cpusta, glintd ; done, enable interrupt 11.4 prescaler assignments timer0 has an 8-bit prescaler. the prescaler assign- ment is fully under software control; i.e., it can be changed ?n the ? during program execution. when changing the prescaler assignment, clearing the pres- caler is recommended before changing assignment. the value of the prescaler is ?nknown, and assigning a value that is less then the present value makes it dif- ?ult to take this unknown time into account. figure 11-4: tmr0 timing: write high or low byte q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale tmr0l tmr0h movfp w,tmr0l write to tmr0l movfp tmr0l,w read tmr0l (value = nt0) movfp tmr0l,w read tmr0l (value = nt0) movfp tmr0l,w read tmr0l (value = nt0 +1) t0 t0+1 new t0 (nt0) new t0+1 pc pc+1 pc+2 pc+3 pc+4 fetch instruction executed
pic17c4x ds30412c-page 70 1996 microchip technology inc. figure 11-5: tmr0 read/write in timer mode table 11-1: registers/bits associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 05h, unbanked t0sta intedg t0se t0cs ps3 ps2 ps1 ps0 0000 000- 0000 000- 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 0bh, unbanked tmr0l tmr0 register; low byte xxxx xxxx uuuu uuuu 0ch, unbanked tmr0h tmr0 register; high byte xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, shaded cells are not used by timer0. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. instruction executed movfp datal,tmr0l write tmr0l movfp datah,tmr0h write tmr0h movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale wr_trm0l wr_tmr0h rd_tmr0l tmr0h tmr0l 12 12 13 ab fe ff 56 57 58 in this example, old tmr0 value is 12feh, new value of ab56h is written. instruction fetched movfp datal,tmr0l write tmr0l movfp datah,tmr0h write tmr0h movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l previously fetched instruction
1996 microchip technology inc. ds30412c-page 71 pic17c4x 12.0 timer1, timer2, timer3, pwms and captures the pic17c4x has a wealth of timers and time-based functions to ease the implementation of control applica- tions. these time-base functions include two pwm out- puts and two capture inputs. timer1 and timer2 are two 8-bit incrementing timers, each with a period register (pr1 and pr2 respectively) and separate over?w interrupt ?gs. timer1 and timer2 can operate either as timers (increment on internal fosc/4 clock) or as counters (increment on fall- ing edge of external clock on pin rb4/tclk12). they are also software con?urable to operate as a single 16-bit timer. these timers are also used as the time-base for the pwm (pulse width modulation) mod- ule. timer3 is a 16-bit timer/counter consisting of the tmr3h and tmr3l registers. this timer has four other associated registers. two registers are used as a 16-bit period register or a 16-bit capture1 register (pr3h/ca1h:pr3l/ca1l). the other two registers are strictly the capture2 registers (ca2h:ca2l). timer3 is the time-base for the two 16-bit captures. tmr3 can be software con?ured to increment from the internal system clock or from an external signal on the rb5/tclk3 pin. figure 12-1 and figure 12-2 are the control registers for the operation of timer1, timer2, and timer3, as well as pwm1, pwm2, capture1, and capture2. figure 12-1: tcon1 register (address: 16h, bank 3) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7-6: ca2ed1:ca2ed0 : capture2 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 5-4: ca1ed1:ca1ed0 : capture1 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 3: t16 : timer1:timer2 mode select bit 1 = timer1 and timer2 form a 16-bit timer 0 = timer1 and timer2 are two 8-bit timers bit 2: tmr3cs : timer3 clock source select bit 1 = tmr3 increments off the falling edge of the rb5/tclk3 pin 0 = tmr3 increments off the internal clock bit 1: tmr2cs : timer2 clock source select bit 1 = tmr2 increments off the falling edge of the rb4/tclk12 pin 0 = tmr2 increments off the internal clock bit 0: tmr1cs : timer1 clock source select bit 1 = tmr1 increments off the falling edge of the rb4/tclk12 pin 0 = tmr1 increments off the internal clock this document was created with framemake r404
pic17c4x ds30412c-page 72 1996 microchip technology inc. figure 12-2: tcon2 register (address: 17h, bank 3) r - 0 r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: ca2ovf : capture2 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca2h:ca2l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the timer3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture2 register 0 = no over?w occurred on capture2 register bit 6: ca1ovf : capture1 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (pr3h/ca2h:pr3l/ca2l) before the next capture event occurred. the capture register retains the old- est unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture1 register 0 = no over?w occurred on capture1 register bit 5: pwm2on : pwm2 on bit 1 = pwm2 is enabled (the rb3/pwm2 pin ignores the state of the ddrb<3> bit) 0 = pwm2 is disabled (the rb3/pwm2 pin uses the state of the ddrb<3> bit for data direction) bit 4: pwm1on : pwm1 on bit 1 = pwm1 is enabled (the rb2/pwm1 pin ignores the state of the ddrb<2> bit) 0 = pwm1 is disabled (the rb2/pwm1 pin uses the state of the ddrb<2> bit for data direction) bit 3: ca1/pr3 : ca1/pr3 register mode select bit 1 = enables capture1 (pr3h/ca1h:pr3l/ca1l is the capture1 register. timer3 runs without a period register) 0 = enables the period register (pr3h/ca1h:pr3l/ca1l is the period register for timer3) bit 2: tmr3on : timer3 on bit 1 = starts timer3 0 = stops timer3 bit 1: tmr2on : timer2 on bit this bit controls the incrementing of the timer2 register. when timer2:timer1 form the 16-bit timer (t16 is set), tmr2on must be set. this allows the msb of the timer to increment. 1 = starts timer2 (must be enabled if the t16 bit (tcon1<3>) is set) 0 = stops timer2 bit 0: tmr1on : timer1 on bit when t16 is set (in 16-bit timer mode) 1 = starts 16-bit timer2:timer1 0 = stops 16-bit timer2:timer1 when t16 is clear (in 8-bit timer mode) 1 = starts 8-bit timer1 0 = stops 8-bit timer1
1996 microchip technology inc. ds30412c-page 73 pic17c4x 12.1 timer1 an d timer2 12.1.1 timer1, timer2 in 8-bit mode both timer1 and timer2 will operate in 8-bit mode when the t16 bit is clear. these two timers can be inde- pendently con?ured to increment from the internal instruction cycle clock or from an external clock source on the rb4/tclk12 pin. the timer clock source is con- ?ured by the tmrxcs bit (x = 1 for timer1 or = 2 for timer2). when tmrxcs is clear, the clock source is internal and increments once every instruction cycle (fosc/4). when tmrxcs is set, the clock source is the rb4/tclk12 pin, and the timer will increment on every falling edge of the rb4/tclk12 pin. the timer increments from 00h until it equals the period register (prx). it then resets to 00h at the next incre- ment cycle. the timer interrupt ?g is set when the timer is reset. tmr1 and tmr2 have individual interrupt ?g bits. the tmr1 interrupt ?g bit is latched into tmr1if, and the tmr2 interrupt ?g bit is latched into tmr2if. each timer also has a corresponding interrupt enable bit (tmrxie). the timer interrupt can be enabled by set- ting this bit and disabled by clearing this bit. for periph- eral interrupts to be enabled, the peripheral interrupt enable bit must be enabled (peie is set) and global interrupts must be enabled (glintd is cleared). the timers can be turned on and off under software control. when the timerx on control bit (tmrxon) is set, the timer increments from the clock source. when tmrxon is cleared, the timer is turned off and cannot cause the timer interrupt ?g to be set. 12.1.1.1 external clock input for timer1 or timer2 when tmrxcs is set, the clock source is the rb4/tclk12 pin, and the timer will increment on every falling edge on the rb4/tclk12 pin. the tclk12 input is synchronized with internal phase clocks. this causes a delay from the time a falling edge appears on tclk12 to the time tmr1 or tmr2 is actually incremented. for the external clock input timing requirements, see the electrical speci?ation section. figure 12-3: timer1 and timer2 in two 8-bit timer/counter mode fosc/4 rb4/tclk12 tmr1on (tcon2<0>) tmr1cs (tcon1<0>) tmr1 pr1 reset equal set tmr1if (pir<4>) 0 1 comparator<8> comparator x8 fosc/4 tmr2on (tcon2<1>) tmr2cs (tcon1<1>) tmr2 pr2 reset equal set tmr2if (pir<5>) 1 0 comparator<8> comparator x8
pic17c4x ds30412c-page 74 1996 microchip technology inc. 12.1.2 timer1 & timer2 in 16-bit mode to select 16-bit mode, the t16 bit must be set. in this mode tmr1 and tmr2 are concatenated to form a 16-bit timer (tmr2:tmr1). the 16-bit timer incre- ments until it matches the 16-bit period register (pr2:pr1). on the following timer clock, the timer value is reset to 0h, and the tmr1if bit is set. when selecting the clock source for the16-bit timer, the tmr1cs bit controls the entire 16-bit timer and tmr2cs is a ?on? care. when tmr1cs is clear, the timer increments once every instruction cycle (fosc/4). when tmr1cs is set, the timer increments on every falling edge of the rb4/tclk12 pin. for the 16-bit timer to increment, both tmr1on and tmr2on bits must be set (table 12-1). 12.1.2.1 external clock input for tmr1:tmr2 when tmr1cs is set, the 16-bit tmr2:tmr1 incre- ments on the falling edge of clock input tclk12. the input on the rb4/tclk12 pin is sampled and synchro- nized by the internal phase clocks twice every instruc- tion cycle. this causes a delay from the time a falling edge appears on rb4/tclk12 to the time tmr2:tmr1 is actually incremented. for the external clock input timing requirements, see the electrical speci?ation section. table 12-1: turning on 16-bit timer tmr2on tmr1on result 11 16-bit timer (tmr2:tmr1) on 01 only tmr1 increments x0 16-bit timer off figure 12-4: tmr1 and tmr2 in 16-bit timer/counter mode table 12-2: summary of timer1 and timer2 registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 10h, bank 2 tmr1 timer1 register xxxx xxxx uuuu uuuu 11h, bank 2 tmr2 timer2 register xxxx xxxx uuuu uuuu 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 14h, bank 2 pr1 timer1 period register xxxx xxxx uuuu uuuu 15h, bank 2 pr2 timer2 period register xxxx xxxx uuuu uuuu 10h, bank 3 pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h, bank 3 pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 12h, bank 3 pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h, bank 3 pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, shaded cells are not used by timer1 or timer2. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset. rb4/tclk12 fosc/4 tmr1on (tcon2<0>) tmr1cs (tcon1<0>) tmr1 x 8 pr1 x 8 reset equal set interrupt tmr1if (pir<4>) 1 0 comparator<8> comparator x16 tmr2 x 8 pr2 x 8
1996 microchip technology inc. ds30412c-page 75 pic17c4x 12.1.3 using pulse width modulation (pwm) outputs with tmr1 and tmr2 two high speed pulse width modulation (pwm) outputs are provided. the pwm1 output uses timer1 as its time-base, while pwm2 may be software con?ured to use either timer1 or timer2 as the time-base. the pwm outputs are on the rb2/pwm1 and rb3/pwm2 pins. each pwm output has a maximum resolution of 10-bits. at 10-bit resolution, the pwm output frequency is 24.4 khz (@ 25 mhz clock) and at 8-bit resolution the pwm output frequency is 97.7 khz. the duty cycle of the output can vary from 0% to 100%. figure 12-5 shows a simpli?d block diagram of the pwm module. the duty cycle register is double buff- ered for glitch free operation. figure 12-6 shows how a glitch could occur if the duty cycle registers were not double buffered. the user needs to set the pwm1on bit (tcon2<4>) to enable the pwm1 output. when the pwm1on bit is set, the rb2/pwm1 pin is con?ured as pwm1 output and forced as an output irrespective of the data direc- tion bit (ddrb<2>). when the pwm1on bit is clear, the pin behaves as a port pin and its direction is con- trolled by its data direction bit (ddrb<2>). similarly, the pwm2on (tcon2<5>) bit controls the con?ura- tion of the rb3/pwm2 pin. figure 12-5: simplified pwm block diagram pwxdch duty cycle registers pwxdcl<7:6> clear timer, pwmx pin and latch d.c. (slave) comparator tmr2 comparator pry (note 1) r s q pwmxon rcy/pwmx note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. read write figure 12-6: pwm output 0 10203040 0 pwm output timer interrupt write new pwm value timer interrupt new pwm value transferred to slave note the dotted line shows pwm output if duty cycle registers were not double buffered. if the new duty cycle is written after the timer has passed that value, then the pwm does not reset at all during the current cycle causing a ?litch? in this example, pwm period = 50. old duty cycle is 30. new duty cycle value is 10.
pic17c4x ds30412c-page 76 1996 microchip technology inc. 12.1.3.1 pwm periods the period of the pwm1 output is determined by timer1 and its period register (pr1). the period of the pwm2 output can be software con?ured to use either timer1 or timer2 as the time-base. when tm2pw2 bit (pw2dcl<5>) is clear, the time-base is determined by tmr1 and pr1. when tm2pw2 is set, the time-base is determined by timer2 and pr2. running two different pwm outputs on two different timers allows different pwm periods. running both pwms from timer1 allows the best use of resources by freeing timer2 to operate as an 8-bit timer. timer1 and timer2 can not be used as a 16-bit timer if either pwm is being used. the pwm periods can be calculated as follows: period of pwm1 =[(pr1) + 1] x 4t osc period of pwm2 =[(pr1) + 1] x 4t osc or [(pr2) + 1] x 4t osc the duty cycle of pwmx is determined by the 10-bit value dcx<9:0>. the upper 8-bits are from register pwxdch and the lower 2-bits are from pwxdcl<7:6> (pwxdch:pwxdcl<7:6>). table 12-3 shows the maximum pwm frequency (f pwm ) given the value in the period register. the number of bits of resolution that the pwm can achieve depends on the operation frequency of the device as well as the pwm frequency (f pwm ). maximum pwm resolution (bits) for a given pwm fre- quency: the pwmx duty cycle is as follows: pwmx duty cycle = (dcx) x t osc where dcx represents the 10-bit value from pwxdch:pwxdcl. if dcx = 0, then the duty cycle is zero. if prx = pwxdch, then the pwm output will be low for one to four q-clock (depending on the state of the pwxdcl<7:6> bits). for a duty cycle to be 100%, the pwxdch value must be greater then the prx value. the duty cycle registers for both pwm outputs are dou- ble buffered. when the user writes to these registers, they are stored in master latches. when tmr1 (or tmr2) over?ws and a new pwm period begins, the master latch values are transferred to the slave latches and the pwmx pin is forced high. note: for pw1dch, pw1dcl, pw2dch and pw2dcl registers, a write operation writes to the "master latches" while a read operation reads the "slave latches". as a result, the user may not read back what was just written to the duty cycle registers. log ( f pwm log (2) f osc ) bits = the user should also avoid any "read-modify-write" operations on the duty cycle registers, such as: addwf pw1dch . this may cause duty cycle outputs that are unpredictable. table 12-3: pwm frequency vs. resolution at 25 mhz 12.1.3.2 pwm interrupts the pwm module makes use of tmr1 or tmr2 inter- rupts. a timer interrupt is generated when tmr1 or tmr2 equals its period register and is cleared to zero. this interrupt also marks the beginning of a pwm cycle. the user can write new duty cycle values before the timer roll-over. the tmr1 interrupt is latched into the tmr1if bit and the tmr2 interrupt is latched into the tmr2if bit. these ?gs must be cleared in soft- ware. 12.1.3.3 external clock source the pwms will operate regardless of the clock source of the timer. the use of an external clock has rami?a- tions that must be understood. because the external tclk12 input is synchronized internally (sampled once per instruction cycle), the time tclk12 changes to the time the timer increments will vary by as much as t cy (one instruction cycle). this will cause jitter in the duty cycle as well as the period of the pwm output. this jitter will be t cy , unless the external clock is syn- chronized with the processor clock. use of one of the pwm outputs as the clock source to the tclkx input, will supply a synchronized clock. in general, when using an external clock source for pwm, its frequency should be much less than the device frequency (fosc). pwm frequency frequency (khz) 24.4 48.8 65.104 97.66 390.6 prx value 0xff 0x7f 0x5f 0x3f 0x0f high resolution 10-bit 9-bit 8.5-bit 8-bit 6-bit standard resolution 8-bit 7-bit 6.5-bit 6-bit 4-bit
1996 microchip technology inc. ds30412c-page 77 pic17c4x 12.1.3.3.1 max resolution/frequency for external clock input the use of an external clock for the pwm time-base (timer1 or timer2) limits the pwm output to a maxi- mum resolution of 8-bits. the pwxdcl<7:6> bits must be kept cleared. use of any other value will distort the pwm output. all resolutions are supported when inter- nal clock mode is selected. the maximum attainable frequency is also lower. this is a result of the timing requirements of an external clock input for a timer (see the electrical speci?ation section). the maximum pwm frequency, when the timers clock source is the rb4/tclk12 pin, is shown in table 12-3 (standard res- olution mode). 12.2 tim er3 timer3 is a 16-bit timer consisting of the tmr3h and tmr3l registers. tmr3h is the high byte of the timer and tmr3l is the low byte. this timer has an associ- ated 16-bit period register (pr3h/ca1h:pr3l/ca1l). this period register can be software con?ured to be a second 16-bit capture register. when the tmr3cs bit (tcon1<2>) is clear, the timer increments every instruction cycle (fosc/4). when tmr3cs is set, the timer increments on every falling edge of the rb5/tclk3 pin. in either mode, the tmr3on bit must be set for the timer to increment. when tmr3on is clear, the timer will not increment or set the tmr3if bit. timer3 has two modes of operation, depending on the ca1/pr3 bit (tcon2<3>). these modes are: one capture and one period register mode dual capture register mode the pic17c4x has up to two 16-bit capture registers that capture the 16-bit value of tmr3 when events are detected on capture pins. there are two capture pins (rb0/cap1 and rb1/cap2), one for each capture reg- ister. the capture pins are multiplexed with portb pins. an event can be: a rising edge a falling edge every 4th rising edge every 16th rising edge each 16-bit capture register has an interrupt ?g asso- ciated with it. the ?g is set when a capture is made. the capture module is truly part of the timer3 block. figure 12-7 and figure 12-8 show the block diagrams for the two modes of operation. table 12-4: registers/bits associated with pwm address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 10h, bank 2 tmr1 timer1 register xxxx xxxx uuuu uuuu 11h, bank 2 tmr2 timer2 register xxxx xxxx uuuu uuuu 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 10h, bank 3 pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h, bank 3 pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 12h, bank 3 pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h, bank 3 pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions, shaded cells are not used by pwm.
pic17c4x ds30412c-page 78 1996 microchip technology inc. 12.2.1 one capture and one period register mode in this mode registers pr3h/ca1h and pr3l/ca1l constitute a 16-bit period register. a block diagram is shown in figure 12-7. the timer increments until it equals the period register and then resets to 0000h. tmr3 interrupt flag bit (tmr3if) is set at this point. this interrupt can be disabled by clearing the tmr3 interrupt enable bit (tmr3ie). tmr3if must be cleared in software. this mode is selected if control bit ca1/pr3 is clear. in this mode, the capture1 register, consisting of high byte (pr3h/ca1h) and low byte (pr3l/ca1l), is con- ?ured as the period control register for tmr3. capture1 is disabled in this mode, and the correspond- ing interrupt bit ca1if is never set. tmr3 increments until it equals the value in the period register and then resets to 0000h. capture2 is active in this mode. the ca2ed1 and ca2ed0 bits determine the event on which capture will occur. the possible events are: capture on every falling edge capture on every rising edge capture every 4th rising edge capture every 16th rising edge when a capture takes place, an interrupt ?g is latched into the ca2if bit. this interrupt can be enabled by set- ting the corresponding mask bit ca2ie. the peripheral interrupt enable bit (peie) must be set and the global interrupt disable bit (glintd) must be cleared for the interrupt to be acknowledged. the ca2if interrupt ?g bit must be cleared in software. when the capture prescale select is changed, the pres- caler is not reset and an event may be generated. therefore, the ?st capture after such a change will be ambiguous. however, it sets the time-base for the next capture. the prescaler is reset upon chip reset. capture pin rb1/cap2 is a multiplexed pin. when used as a port pin, capture2 is not disabled. however, the user can simply disable the capture2 interrupt by clear- ing ca2ie. if rb1/cap2 is used as an output pin, the user can activate a capture by writing to the port pin. this may be useful during development phase to emu- late a capture interrupt. the input on capture pin rb1/cap2 is synchronized internally to internal phase clocks. this imposes certain restrictions on the input waveform (see the electrical speci?ation section for timing). the capture2 over?w status ?g bit is double buff- ered. the master bit is set if one captured word is already residing in the capture2 register and another ?vent has occurred on the rb1/ca2 pin. the new event will not transfer the timer3 value to the capture register, protecting the previous unread capture value. when the user reads both the high and the low bytes (in any order) of the capture2 register, the master over?w bit is transferred to the slave over?w bit (ca2ovf) and then the master bit is reset. the user can then read tcon2 to determine the value of ca2ovf. the recommended sequence to read capture registers and capture over?w ?g bits is shown in example 12-1. example 12-1: sequence to read capture registers movlb 3 ;select bank 3 movpf ca2l,lo_byte ;read capture2 low ;byte, store in lo_byte movpf ca2h,hi_byte ;read capture2 high ;byte, store in hi_byte movpf tcon2,stat_val ;read tcon2 into file ;stat_val figure 12-7: timer3 with one capture and one period register block diagram pr3h/ca1h tmr3h comparator<8> fosc/4 tmr3on reset equal 0 1 comparator x16 rb5/tclk3 set tmr3if tmr3cs pr3l/ca1l tmr3l ca2h ca2l rb1/cap2 edge select prescaler select 2 set ca2if capture1 enable ca2ed1: ca2ed0 (tcon1<7:6>) (tcon2<2>) (tcon1<2>) (pir<3>) (pir<6>)
1996 microchip technology inc. ds30412c-page 79 pic17c4x 12.2.2 dual capture register mode this mode is selected by setting ca1/pr3 . a block dia- gram is shown in figure 12-8. in this mode, tmr3 runs without a period register and increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt flag (tmr3if) is set on this roll over. the tmr3if bit must be cleared in software. registers pr3h/ca1h and pr3l/ca1l make a 16-bit capture register (capture1). it captures events on pin rb0/cap1. capture mode is con?ured by the ca1ed1 and ca1ed0 bits. capture1 interrupt flag bit (ca1if) is set on the capture event. the corresponding interrupt mask bit is ca1ie. the capture1 over?w status bit is ca1ovf. the capture2 over?w status ?g bit is double buff- ered. the master bit is set if one captured word is already residing in the capture2 register and another ?vent has occurred on the rb1/ca2 pin. the new event will not transfer the tmr3 value to the capture register which protects the previous unread capture value. when the user reads both the high and the low bytes (in any order) of the capture2 register, the master over?w bit is transferred to the slave over?w bit (ca2ovf) and then the master bit is reset. the user can then read tcon2 to determine the value of ca2ovf. the operation of the capture1 feature is identical to capture2 (as described in section 12.2.1). figure 12-8: timer3 with two capture registers block diagram table 12-5: registers associated with capture address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 12h, bank 2 tmr3l tmr3 register; low byte xxxx xxxx uuuu uuuu 13h, bank 2 tmr3h tmr3 register; high byte xxxx xxxx uuuu uuuu 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 16h, bank 2 pr3l/ca1l timer3 period register, low byte/capture1 register, low byte xxxx xxxx uuuu uuuu 17h, bank 2 pr3h/ca1h timer3 period register, high byte/capture1 register, high byte xxxx xxxx uuuu uuuu 14h, bank 3 ca2l capture2 low byte xxxx xxxx uuuu uuuu 15h, bank 3 ca2h capture2 high byte xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by capture. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset. 2 rb0/cap1 edge select prescaler select pr3h/ca1h pr3l/ca1l tmr3h tmr3l rb5/tclk3 0 1 fosc/4 rb1/cap2 edge select prescaler select 2 ca2ed1, ca2ed0 (tcon1<7:6>) ca2h ca2l set ca2if (pir<3>) set tmr3if (pir<6>) set ca1if (pir<2>) capture enable capture enable tmr3on (tcon2<2>) tmr3cs (tcon1<2>) ca1ed1, ca1ed0 (tcon1<5:4>)
pic17c4x ds30412c-page 80 1996 microchip technology inc. 12.2.3 external clock input for timer3 when tmr3cs is set, the 16-bit tmr3 increments on the falling edge of clock input tclk3. the input on the rb5/tclk3 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. this causes a delay from the time a falling edge appears on tclk3 to the time tmr3 is actually incremented. for the external clock input timing requirements, see the electrical speci?ation section. figure 12-9 shows the timing diagram when operating from an external clock. 12.2.4 reading/writing timer3 since timer3 is a 16-bit timer and only 8-bits at a time can be read or written, care should be taken when reading or writing while the timer is running. the best method to read or write the timer is to stop the timer, perform any read or write operation, and then restart timer3 (using the tmr3on bit). however, if it is neces- sary to keep timer3 free-running, care must be taken. for writing to the 16-bit tmr3, example 12-2 may be used. for reading the 16-bit tmr3, example 12-3 may be used. interrupts must be disabled during this rou- tine. example 12-2: writing to tmr3 bsf cpusta, glintd ;disable interrupt movfp ram_l, tmr3l ; movfp ram_h, tmr3h ; bcf cpusta, glintd ;done,enable interrupt example 12-3: reading from tmr3 movpf tmr3l, tmplo ;read low tmr0 movpf tmr3h, tmphi ;read high tmr0 movfp tmplo, wreg ;tmplo -> wreg cpfslt tmr3l, wreg ;tmr0l < wreg? return ;no then return movpf tmr3l, tmplo ;read low tmr0 movpf tmr3h, tmphi ;read high tmr0 return ;return figure 12-9: tmr1, tmr2, and tmr3 operation in external clock mode q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction executed movwf movfp tmrx,w tmrx movfp tmrx,w write to tmrx read tmrx read tmrx 34h 35h a8h a9h 00h 'a9h' 'a9h' tclk12 tmr1, tmr2, or tmr3 pr1, pr2, or pr3h:pr3l wr_tmr read_tmr tmrxif note 1: tclk12 is sampled in q2 and q4. 2: indicates a sampling point. 3: the latency from tclk12 to timer increment is between 2tosc and 6tosc.
1996 microchip technology inc. ds30412c-page 81 pic17c4x figure 12-10: tmr1, tmr2, and tmr3 operation in timer mode table 12-6: summary of tmr1, tmr2, and tmr3 registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 10h, bank 2 tmr1 timer1 register xxxx xxxx uuuu uuuu 11h, bank 2 tmr2 timer2 register xxxx xxxx uuuu uuuu 12h, bank 2 tmr3l tmr3 register; low byte xxxx xxxx uuuu uuuu 13h, bank 2 tmr3h tmr3 register; high byte xxxx xxxx uuuu uuuu 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- 14h, bank 2 pr1 timer1 period register xxxx xxxx uuuu uuuu 15h, bank 2 pr2 timer2 period register xxxx xxxx uuuu uuuu 16h, bank 2 pr3l/ca1l timer3 period/capture1 register; low byte xxxx xxxx uuuu uuuu 17h, bank 2 pr3h/ca1h timer3 period/capture1 register; high byte xxxx xxxx uuuu uuuu 10h, bank 3 pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h, bank 3 pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 12h, bank 3 pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h, bank 3 pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 14h, bank 3 ca2l capture2 low byte xxxx xxxx uuuu uuuu 15h, bank 3 ca2h capture2 high byte xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by tmr1, tmr2 or tmr3. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale instruction fetched tmr1 pr1 tmr1on wr_tmr1 wr_tcon2 tmr1if rd_tmr1 tmr1 reads 03h tmr1 reads 04h movwf tmr1 write tmr1 movf tmr1, w read tmr1 movf tmr1, w read tmr1 bsf tcon2, 0 stop tmr1 bcf tcon2, 0 start tmr1 movlb 3 nop nop nop nop nop 04h 05h 03h 04h 05h 06h 07h 08h 00h
pic17c4x ds30412c-page 82 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 83 pic17c4x 13.0 universal synchronous asynchronous receiver transmitter (usart) module the usart module is a serial i/o module. the usart can be con?ured as a full duplex asynchronous sys- tem that can communicate with peripheral devices such as crt terminals and personal computers, or it can be con?ured as a half duplex synchronous system that can communicate with peripheral devices such as a/d or d/a integrated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) the spen (rcsta<7>) bit has to be set in order to con?ure ra4 and ra5 as the serial communication interface. the usart module will control the direction of the ra4/rx/dt and ra5/tx/ck pins, depending on the states of the usart con?uration bits in the rcsta and txsta registers. the bits that control i/o direction are: spen txen sren cren csrc the transmit status and control register is shown in figure 13-1, while the receive status and control register is shown in figure 13-2. figure 13-1: txsta register (address: 15h, bank 0) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 u - 0 r - 1 r/w - x csrc tx9 txen sync trmt tx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7: csrc : clock source select bit synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) asynchronous mode : don? care bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled sren/cren overrides txen in sync mode bit 4: sync : usart mode select bit (synchronous/asynchronous) 1 = synchronous mode 0 = asynchronous mode bit 3-2: unimplemented : read as '0' bit 1: trmt : transmit shift register (tsr) empty bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data (can be used to calculated the parity in software) this document was created with framemake r404
pic17c4x ds30412c-page 84 1996 microchip technology inc. figure 13-2: rcsta register (address: 13h, bank 0) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 r - 0 r - 0 r - x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit 0 bit 7: spen : serial port enable bit 1 = con?ures ra5/rx/dt and ra4/tx/ck pins as serial port pins 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit this bit enables the reception of a single byte. after receiving the byte, this bit is automatically cleared. synchronous mode: 1 = enable reception 0 = disable reception note: this bit is ignored in synchronous slave reception. a synchronous mode: don? care bit 4: cren : continuous receive enable bit this bit enables the continuous reception of serial data. asynchronous mode: 1 = enable reception 0 = disables reception synchronous mode: 1 = enables continuous reception until cren is cleared (cren overrides sren) 0 = disables continuous reception bit 3: unimplemented : read as '0' bit 2: ferr : framing error bit 1 = framing error (updated by reading rcreg) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun (cleared by clearing cren) 0 = no overrun error bit 0: rx9d : 9th bit of receive data (can be the software calculated parity bit)
1996 microchip technology inc. ds30412c-page 85 pic17c4x figure 13-3: usart transmit figure 13-4: usart receive ck/tx dt sync/async tsr start 0 1 7 8 stop ?? 16 4 brg 01 7 ?? 8 bit count txie interrupt txen/ write to txreg clock sync/async sync/async txsta<0> sync master/slave data bus load txreg ck rx 0 1 7 8 stop ?? 16 4 brg bit count clock buffer logic buffer logic spen osc start 0 1 7 rx9d ?? 0 1 7 rx9d ?? ferr ferr majority detect data msb lsb rsr rcreg async/sync sync/async master/slave sync enable fifo logic clk fifo rcie interrupt rx9 data bus sren/ cren/ start_bit async/sync detect
pic17c4x ds30412c-page 86 1996 microchip technology inc. 13.1 usar t b aud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. table 13-1 shows the formula for computation of the baud rate for differ- ent usart modes. these only apply when the usart is in synchronous master mode (internal clock) and asynchronous mode. given the desired baud rate and fosc, the nearest inte- ger value between 0 and 255 can be calculated using the formula below. the error in baud rate can then be determined. table 13-1: baud rate formula sync mode baud rate 0 1 asynchronous synchronous f osc /(64(x+1)) f osc /(4(x+1)) x = value in spbrg (0 to 255) example 13-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 sync = 0 example 13-1: calculating baud rate error writing a new value to the spbrg, causes the brg timer to be reset (or cleared), this ensures that the brg does not wait for a timer over?w before outputting the new baud rate. desired baud rate=fosc / (64 (x + 1)) 9600 = 16000000 /(64 (x + 1)) x = 25.042 = 25 calculated baud rate=16000000 / (64 (25 + 1)) = 9615 error = ( calculated b aud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% table 13-2: registers associated with baud rate generator address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the baud rate generator. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1996 microchip technology inc. ds30412c-page 87 pic17c4x table 13-3: baud rates for synchronous mode baud rate (k) f osc = 33 mhz spbrg value (decimal) f osc = 25 mhz spbrg value (decimal) f osc = 20 mhz spbrg value (decimal) f osc = 16 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na na na na 1.2 na na na na 2.4 na na na na 9.6 na na na na 19.2 na na 19.53 +1.73 255 19.23 +0.16 207 76.8 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 76.92 +0.16 51 96 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 95.24 -0.79 41 300 294.64 -1.79 27 297.62 -0.79 20 294.1 -1.96 16 307.69 +2.56 12 500 485.29 -2.94 16 480.77 -3.85 12 500 0 9 500 0 7 high 8250 0 6250 0 5000 0 4000 0 low 32.22 255 24.41 255 19.53 255 15.625 255 baud rate (k) f osc = 10 mhz spbrg value (decimal) f osc = 7.159 mhz spbrg value (decimal) f osc = 5.068 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na na 1.2 na na na 2.4 na na na 9.6 9.766 +1.73 255 9.622 +0.23 185 9.6 0 131 19.2 19.23 +0.16 129 19.24 +0.23 92 19.2 0 65 76.8 75.76 -1.36 32 77.82 +1.32 22 79.2 +3.13 15 96 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 312.5 +4.17 7 298.3 -0.57 5 316.8 +5.60 3 500 500 0 4 na ?a high 2500 0 1789.8 0 1267 0 low 9.766 255 6.991 255 4.950 255 baud rate (k) f osc = 3.579 mhz spbrg value (decimal) f osc = 1 mhz spbrg value (decimal) f osc = 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na 0.303 +1.14 26 1.2 na 1.202 +0.16 207 1.170 -2.48 6 2.4 na 2.404 +0.16 103 na 9.6 9.622 +0.23 92 9.615 +0.16 25 na 19.2 19.04 -0.83 46 19.24 +0.16 12 na 76.8 74.57 -2.90 11 83.34 +8.51 2 na 96 99.43 _3.57 8 na na 300 298.3 -0.57 2 na na 500 na na na high 894.9 0 250 0 8.192 0 low 3.496 255 0.976 255 0.032 255
pic17c4x ds30412c-page 88 1996 microchip technology inc. table 13-4: baud rates for asynchronous mode baud rate (k) f osc = 33 mhz spbrg value (decimal) f osc = 25 mhz spbrg value (decimal) f osc = 20 mhz spbrg value (decimal) f osc = 16 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na na na na 1.2 na na 1.221 +1.73 255 1.202 +0.16 207 2.4 2.398 -0.07 214 2.396 0.14 162 2.404 +0.16 129 2.404 +0.16 103 9.6 9.548 -0.54 53 9.53 -0.76 40 9.469 -1.36 32 9.615 +0.16 25 19.2 19.09 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 19.23 +0.16 12 76.8 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 83.33 +8.51 2 96 103.12 +7.42 4 97.65 +1.73 3 104.2 +8.51 2 na 300 257.81 -14.06 1 390.63 +30.21 0 312.5 +4.17 0 na 500 515.62 +3.13 0 na na na high 515.62 0 0 312.5 0 250 0 low 2.014 255 1.53 255 1.221 255 0.977 255 baud rate (k) f osc = 10 mhz spbrg value (decimal) f osc = 7.159 mhz spbrg value (decimal) f osc = 5.068 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na 0.31 +3.13 255 1.2 1.202 +0.16 129 1.203 _0.23 92 1.2 0 65 2.4 2.404 +0.16 64 2.380 -0.83 46 2.4 0 32 9.6 9.766 +1.73 15 9.322 -2.90 11 9.9 -3.13 7 19.2 19.53 +1.73 7 18.64 -2.90 5 19.8 +3.13 3 76.8 78.13 +1.73 1 na 79.2 +3.13 0 96 na na na 300 na na na 500 na na na high 156.3 0 111.9 0 79.2 0 low 0.610 255 0.437 255 0.309 2 55 baud rate (k) f osc = 3.579 mhz spbrg value (decimal) f osc = 1 mhz spbrg value (decimal) f osc = 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.190 -0.83 46 1.202 +0.16 12 na 2.4 2.432 +1.32 22 2.232 -6.99 6 na 9.6 9.322 -2.90 5 na na 19.2 18.64 -2.90 2 na na 76.8 na na na 96 na na na 300 na na na 500 na na na high 55.93 0 15.63 0 0.512 0 low 0.218 255 0.061 255 0.002 255
1996 microchip technology inc. ds30412c-page 89 pic17c4x 13.2 usar t a sync hr onous mode in this mode, the usart uses standard nonre- turn-to-zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data for- mat is 8-bits. an on-chip dedicated 8-bit baud rate gen- erator can be used to derive standard baud rate frequencies from the oscillator. the usarts transmit- ter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock x64 of the bit shift rate. par- ity is not supported by the hardware, but can be imple- mented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. the asynchronous mode is selected by clearing the sync bit (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 13.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 13-3. the heart of the transmitter is the transmit shift register (tsr). the shift register obtains its data from the read/write transmit buffer (txreg). txreg is loaded with data in software. the tsr is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg (if available). once txreg transfers the data to the tsr (occurs in one t cy at the end of the current brg cycle), the txreg is empty and an interrupt bit, txif (pir<1>) is set. this interrupt can be enabled or disabled by the txie bit (pie<1>). txif will be set regardless of txie and cannot be reset in software. it will reset only when new data is loaded into txreg. while txif indicates the status of the txreg, the trmt (txsta<1>) bit shows the status of the tsr. trmt is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr is empty. note: the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting the txen (txsta<5>) bit. the actual transmission will not occur until txreg has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 13-5). the transmission can also be started by ?st loading txreg and then setting txen. normally when transmission is ?st started, the tsr is empty, so a transfer to txreg will result in an immediate transfer to tsr resulting in an empty txreg. a back-to-back transfer is thus possible (figure 13-6). clearing txen during a transmission will cause the transmission to be aborted. this will reset the transmitter and the ra5/tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg. this is because a data write to txreg can result in an immediate transfer of the data to the tsr (if the tsr is empty). steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, then set the txie bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. load data to the txreg register. 6. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 7. enable the transmission by setting txen (starts transmission). writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner then doing these two events in the opposite order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled.
pic17c4x ds30412c-page 90 1996 microchip technology inc. figure 13-5: asynchronous master transmission figure 13-6: asynchronous master transmission (back to back) table 13-5: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 0 txreg serial port transmit register xxxx xxxx uuuu uuuu 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx txif bit trmt bit (ra5/tx/ck pin) transmit shift reg. write to txreg brg output (shift clock) tx txif bit trmt bit word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. (ra5/tx/ck pin)
1996 microchip technology inc. ds30412c-page 91 pic17c4x 13.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 13-4. the data comes in the ra4/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at 16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg (if it is empty). if the transfer is complete, the interrupt bit rcif (pir<0>) is set. the actual interrupt can be enabled/disabled by setting/clearing the rcie (pie<0>) bit. rcif is a read only bit which is cleared by the hardware. it is cleared when rcreg has been read and is empty. rcreg is a double buffered regis- ter; (i.e. it is a two deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte begin shifting to the rsr. on detection of the stop bit of the third byte, if the rcreg is still full, then the overrun error bit, oerr (rcsta<1>) will be set. the word in the rsr will be lost. rcreg can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in software which is done by resetting the receive logic (cren is set). if the oerr bit is set, transfers from the rsr to rcreg are inhibited, so it is essential to clear the oerr bit if it is set. the framing error bit ferr (rcsta<2>) is set if a stop bit is not detected. 13.2.3 sampling the data on the ra4/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the ra4/rx/dt pin. the sam- pling is done on the seventh, eighth and ninth falling edges of a x16 clock (figure 11-3). the x16 clock is a free running clock, and the three sample points occur at a frequency of every 16 falling edges. note: the ferr and the 9th receive bit are buff- ered the same way as the receive data. reading the rcreg register will allow the rx9d and ferr bits to be loaded with val- ues for the next received received data; therefore, it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old ferr and rx9d information. figure 13-7: rx pin sampling scheme rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (ra4/rx/dt pin)
pic17c4x ds30412c-page 92 1996 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, then set the rcie bit. 4. if 9-bit reception is desired, then set the rx9 bit. 5. enable the reception by setting the cren bit. 6. the rcif bit will be set when reception com- pletes and an interrupt will be generated if the rcie bit was set. 7. read rcsta to get the ninth bit (if enabled) and ferr bit to determine if any error occurred dur- ing reception. 8. read rcreg for the 8-bit received data. 9. if an overrun error occurred, clear the error by clearing the oerr bit. note: to terminate a reception, either clear the sren and cren bits, or the spen bit. this will reset the receive logic, so that it will be in the proper state when receive is re-enabled. figure 13-8: asynchronous reception table 13-6: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 0 rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. (ra4/rx/dt pin) word 3
1996 microchip technology inc. ds30412c-page 93 pic17c4x 13.3 usar t s ync hr onous master mode in master synchronous mode, the data is transmitted in a half-duplex manner; i.e. transmission and reception do not occur at the same time: when transmitting data, the reception is inhibited and vice versa. the synchro- nous mode is entered by setting the sync (txsta<4>) bit. in addition, the spen (rcsta<7>) bit is set in order to con?ure the ra5 and ra4 i/o ports to ck (clock) and dt (data) lines respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting the csrc (txsta<7>) bit. 13.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 13-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer txreg. txreg is loaded with data in software. the tsr is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from txreg (if available). once txreg transfers the data to the tsr (occurs in one t cy at the end of the current brg cycle), txreg is empty and the txif (pir<1>) bit is set. this interrupt can be enabled/disabled by setting/clearing the txie bit (pie<1>). txif will be set regardless of the state of bit txie and cannot be cleared in software. it will reset only when new data is loaded into txreg. while txif indicates the status of txreg, trmt (txsta<1>) shows the status of the tsr. trmt is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting the txen (txsta<5>) bit. the actual transmission will not occur until txreg has been loaded with data. the ?st data bit will be shifted out on the next available rising edge of the clock on the ra5/tx/ck pin. data out is stable around the falling edge of the synchronous clock (figure 13-10). the transmission can also be started by ?st loading txreg and then setting txen. this is advantageous when slow baud rates are selected, since brg is kept in reset when the txen, cren, and sren bits are clear. setting the txen bit will start the brg, creating a shift clock immediately. normally when transmission is ?st started, the tsr is empty, so a transfer to txreg will result in an immediate transfer to the tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing txen during a transmission will cause the transmission to be aborted and will reset the transmit- ter. the ra4/rx/dt and ra5/tx/ck pins will revert to hi-impedance. if either cren or sren are set during a transmission, the transmission is aborted and the ra4/rx/dt pin reverts to a hi-impedance state (for a reception). the ra5/tx/ck pin will remain an output if the csrc bit is set (internal clock). the transmitter logic is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear the txen bit. if the sren bit is set (to interrupt an ongoing transmission and receive a single word), then after the single word is received, sren will be cleared and the serial port will revert back to transmitting, since the txen bit is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driving. to avoid this, txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to txreg. this is because a data write to txreg can result in an immediate transfer of the data to the tsr (if the tsr is empty). if the tsr was empty and txreg was written before writing the ?ew tx9d, the ?resent value of tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (see baud rate generator section for details). 2. enable the synchronous master serial port by setting the sync, spen, and csrc bits. 3. ensure that the cren and sren bits are clear (these bits override transmission when set). 4. if interrupts are desired, then set the txie bit (the glintd bit must be clear and the peie bit must be set). 5. if 9-bit transmission is desired, then set the tx9 bit. 6. start transmission by loading data to the txreg register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 8. enable the transmission by setting txen. writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner then doing these two events in the reverse order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled.
pic17c4x ds30412c-page 94 1996 microchip technology inc. table 13-7: registers associated with synchronous master transmission figure 13-9: synchronous transmission figure 13-10: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 0 txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous master transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q3 q4 dt ck write to txreg txif interrupt ?g trmt txen '1' note: sync master mode; brg = 0. continuous transmission of two 8-bit words. write word 1 write word 2 bit0 bit1 bit2 bit7 bit0 word 1 word 2 (ra4/rx/dt pin) (ra5/tx/ck pin) dt ck write to txreg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 (ra4/rx/dt pin) (ra5/tx/ck pin)
1996 microchip technology inc. ds30412c-page 95 pic17c4x 13.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the sren (rcsta<5>) bit or the cren (rcsta<4>) bit. data is sampled on the ra4/rx/dt pin on the falling edge of the clock. if sren is set, then only a single word is received. if cren is set, the reception is continuous until cren is reset. if both bits are set, then cren takes prece- dence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to rcreg (if it is empty). if the transfer is complete, the interrupt bit rcif (pir<0>) is set. the actual interrupt can be enabled/disabled by setting/clearing the rcie (pie<0>) bit. rcif is a read only bit which is reset by the hardware. in this case it is reset when rcreg has been read and is empty. rcreg is a dou- ble buffered register; i.e., it is a two deep fifo. it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte to begin shifting into the rsr. on the clocking of the last bit of the third byte, if rcreg is still full, then the overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. rcreg can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in software. this is done by clearing the cren bit. if oerr bit is set, transfers from rsr to rcreg are inhibited, so it is essential to clear oerr bit if it is set. the 9th receive bit is buffered the same way as the receive data. reading the rcreg register will allow the rx9d and ferr bits to be loaded with values for the next received data; therefore, it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old ferr and rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. see section 13.1 for details. 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set the rcie bit. 4. if 9-bit reception is desired, then set the rx9 bit. 5. if a single reception is required, set bit sren. for continuous reception set bit cren. 6. the rcif bit will be set when reception is com- plete and an interrupt will be generated if the rcie bit was set. 7. read rcsta to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading rcreg. 9. if any error occurred, clear the error by clearing cren. note: to terminate a reception, either clear the sren and cren bits, or the spen bit. this will reset the receive logic, so that it will be in the proper state when receive is re-enabled. figure 13-11: synchronous reception (master mode, sren) cren bit dt ck write to the sren bit sren bit rcif bit read rcreg note: timing diagram demonstrates sync master mode with sren = 1. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4 (ra4/rx/dt pin) (ra5/tx/ck pin)
pic17c4x ds30412c-page 96 1996 microchip technology inc. table 13-8: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 0 rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous master reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1996 microchip technology inc. ds30412c-page 97 pic17c4x 13.4 usar t s ync hr onous sla ve mode the synchronous slave mode differs from the master mode in the fact that the shift clock is supplied exter- nally at the ra5/tx/ck pin (instead of being supplied internally in the master mode). this allows the device to transfer or receive data in the sleep mode. the slave mode is entered by clearing the csrc (txsta<7>) bit. 13.4.1 usart synchronous slave transmit the operation of the sync master and slave modes are identical except in the case of the sleep mode. if two words are written to txreg and then the sleep instruction executes, the following will occur. the ?st word will immediately transfer to the tsr and will trans- mit as the shift clock is supplied. the second word will remain in txreg. txif will not be set. when the ?st word has been shifted out of tsr, txreg will transfer the second word to the tsr and the txif ?g will now be set. if txie is enabled, the interrupt will wake the chip from sleep and if the global interrupt is enabled, then the program will branch to interrupt vector (0020h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting the sync and spen bits and clearing the csrc bit. 2. clear the cren bit. 3. if interrupts are desired, then set the txie bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. start transmission by loading data to txreg. 6. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 7. enable the transmission by setting txen. writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner then doing these two events in the reverse order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled. 13.4.2 usart synchronous slave reception operation of the synchronous master and slave modes are identical except in the case of the sleep mode. also, sren is a don't care in slave mode. if receive is enabled (cren) prior to the sleep instruc- tion, then a word may be received during sleep. on completely receiving the word, the rsr will transfer the data to rcreg (setting rcif) and if the rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0020h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting the sync and spen bits and clearing the csrc bit. 2. if interrupts are desired, then set the rcie bit. 3. if 9-bit reception is desired, then set the rx9 bit. 4. to enable reception, set the cren bit. 5. the rcif bit will be set when reception is com- plete and an interrupt will be generated if the rcie bit was set. 6. read rcsta to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading rcreg. 8. if any error occurred, clear the error by clearing the cren bit. note: to abort reception, either clear the spen bit, the sren bit (when in single receive mode), or the cren bit (when in continu- ous receive mode). this will reset the receive logic, so that it will be in the proper state when receive is re-enabled.
pic17c4x ds30412c-page 98 1996 microchip technology inc. table 13-9: registers associated with synchronous slave transmission table 13-10: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank 1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank 0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 0 txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 17h, bank 1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous slave transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) 16h, bank1 pir rbif tmr3if tmr2if tmr1if ca2if ca1if txif rcif 0000 0010 0000 0010 13h, bank0 rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank0 rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 17h, bank1 pie rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie txie rcie 0000 0000 0000 0000 15h, bank 0 txsta csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank0 spbrg baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous slave reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1996 microchip technology inc. ds30412c-page 99 pic17c4x 14.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real time applications. the pic17cxx family has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) interrupts watchdog timer (wdt) sleep code protection the pic17cxx has a watchdog timer which can be shut off only through eprom bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscil- lator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 96 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabi- lizes. with these two timers on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low cur- rent power-down mode. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. several oscillator options are also made available to allow the part to ? the applica- tion. the rc oscillator option saves system cost while the lf crystal option saves power. con?uration bits are used to select various options. this con?uration word has the format shown in figure 14-1. figure 14-1: configuration word r/p - 1 u - x u - x u - x u - x u - x u - x u - x pm2 (1) bit15-7 bit0 u - x r/p - 1 u - x r/p - 1 r/p - 1 r/p - 1 r/p - 1 r/p - 1 pm1 pm0 wdtps1 wdtps0 fosc1 fosc0 r = readable bit p = programmable bit u = unimplemented - n = value for erased device (x = unknown) bit15-7 bit0 bit 15-9: unimplemented : read as a '1' bit 15,6,4: pm2, pm1, pm0 , processor mode select bits 111 = microprocessor mode 110 = microcontroller mode 101 = extended microcontroller mode 000 = code protected microcontroller mode bit 7, 5: unimplemented : read as a '0' bit 3-2: wdtps1:wdtps0 , wdt postscaler select bits 11 = wdt enabled, postscaler = 1 10 = wdt enabled, postscaler = 256 01 = wdt enabled, postscaler = 64 00 = wdt disabled, 16-bit over?w timer bit 1-0: fosc1:fosc0 , oscillator select bits 11 = ec oscillator 10 = xt oscillator 01 = rc oscillator 00 = lf oscillator note 1: this bit does not exist on the pic17c42. reading this bit will return an unknown value (x). this document was created with framemake r404
pic17c4x ds30412c-page 100 1996 microchip technology inc. 14.1 con guratio n bits the pic17cxx has up to seven con?uration locations (table 14-1). these locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. any write to a con?ura- tion location, regardless of the data, will program that con?uration bit. a tablwt instruction is required to write to program memory locations. the con?uration bits can be read by using the tablrd instructions. reading any con?uration location between fe00h and fe07h will read the low byte of the con?uration word (figure 14-1) into the tablatl register. the tab- lath register will be ffh. reading a con?uration location between fe08h and fe0fh will read the high byte of the con?uration word into the tablatl regis- ter. the tablath register will be ffh. addresses fe00h thorough fe0fh are only in the pro- gram memory space for microcontroller and code pro- tected microcontroller modes. a device programmer will be able to read the con?uration word in any pro- cessor mode. see programming speci?ations for more detail. table 14-1: configuration locations bit address fosc0 fe00h fosc1 fe01h wdtps0 fe02h wdtps1 fe03h pm0 fe04h pm1 fe06h pm2 (1) fe0fh (1) note 1: this location does not exist on the pic17c42. note: when programming the desired con?ura- tion locations, they must be programmed in ascending order. starting with address fe00h. 14.2 oscillator con gurations 14.2.1 oscillator types the pic17cxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1:fosc0) to select one of these four modes: lf: low power crystal xt: crystal/resonator ec: external clock input rc: resistor/capacitor 14.2.2 crystal oscillator / ceramic resonators in xt or lf modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 14-2). the pic17cxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?a- tions. for frequencies above 20 mhz, it is common for the crystal to be an overtone mode crystal. use of overtone mode crystals require a tank circuit to attenuate the gain at the fundamental frequency. figure 14-3 shows an example of this. figure 14-2: crystal or ceramic resonator operation (xt or lf osc configuration) see table 14-2 and table 14-3 for recommended values of c1 and c2. note 1: a series resistor may be required for at strip cut crystals. c1 c2 xtal osc2 note1 osc1 rf sleep pic17cxx to internal logic
1996 microchip technology inc. ds30412c-page 101 pic17c4x figure 14-3: crystal operation, overtone crystals (xt osc configuration) table 14-2: capacitor selection for ceramic resonators oscillator type resonator frequency capacitor range c1 = c2 lf 455 khz 2.0 mhz 15 - 68 pf 10 - 33 pf xt 4.0 mhz 8.0 mhz 16.0 mhz 22 - 68 pf 33 - 100 pf 33 - 100 pf higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each reso- nator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% resonators used did not have built-in capacitors. c1 c2 0.1 m f sleep osc2 osc1 pic17c42 to ?ter the fundamental frequency 1 lc2 = (2 p f) 2 where f = tank circuit resonant frequency. this should be midway between the fundamental and the 3rd overtone frequencies of the crystal. table 14-3: capacitor selection for crystal oscillator 14.2.3 external clock oscillator in the ec oscillator mode, the osc1 input can be driven by cmos drivers. in this mode, the osc1/clkin pin is hi-impedance and the osc2/clk- out pin is the clkout output (4 t osc ). figure 14-4: external clock input operation (ec osc configuration) osc type freq c1 c2 lf 32 khz (1) 1 mhz 2 mhz 100-150 pf 10-33 pf 10-33 pf 100-150 pf 10-33 pf 10-33 pf xt 2 mhz 4 mhz 8 mhz (2) 16 mhz 25 mhz 32 mhz (3) 47-100 pf 15-68 pf 15-47 pf tbd 15-47 pf 0 (3) 47-100 pf 15-68 pf 15-47 pf tbd 15-47 pf 0 (3) higher capacitance increases the stability of the oscillator but also increases the start-up time and the oscillator current. these values are for design guid- ance only. r s may be required in xt mode to avoid overdriving the crystals with low drive level speci?a- tion. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values for external components. note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recom- mended. 2: r s of 330 w is required for a capacitor com- bination of 15/15 pf. 3: only the capacitance of the board was present. crystals used: 32.768 khz epson c-001r32.768k-a 20 ppm 1.0 mhz ecs-10-13-1 50 ppm 2.0 mhz ecs-20-20-1 50 ppm 4.0 mhz ecs-40-20-1 50 ppm 8.0 mhz ecs ecs-80-s-4 ecs-80-18-1 50 ppm 16.0 mhz ecs-160-20-1 tbd 25 mhz cts cts25m 50 ppm 32 mhz crystek hf-2 50 ppm clock from ext. system osc1 osc2 pic17cxx clkout (f osc /4)
pic17c4x ds30412c-page 102 1996 microchip technology inc. 14.2.4 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepack- aged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. figure 14-5 shows implementation of a parallel reso- nant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a par- allel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiometer biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 14-5: external parallel resonant crystal oscillator circuit figure 14-6 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 k w resistors provide the negative feed- back to bias the inverters in their linear region. figure 14-6: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic17cxx osc1 to other devices 330 k w 74as04 74as04 pic17cxx osc1 to other devices xtal 330 k w 74as04 0.1 m f 14.2.5 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. rc oscillator fre- quency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 14-6 shows how the r/c combination is con- nected to the pic17cxx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with little or no external capacitance, oscillation frequency can vary dramatically due to changes in external capaci- tances, such as pcb trace capacitance or package lead frame capacitance. see section 18.0 for rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc fre- quency more). see section 18.0 for variation of oscillator frequency due to v dd for given rext/cext values as well as fre- quency variation due to operating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 3-2 for waveform). figure 14-7: rc oscillator mode v dd rext cext v ss osc1 internal clock osc2/clkout fosc/4 pic17cxx
1996 microchip technology inc. ds30412c-page 103 pic17c4x 14.3 w atc hdog timer (wdt) the watchdog timers function is to recover from soft- ware malfunction. the wdt uses an internal free run- ning on-chip rc oscillator for its clock source. this does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clk- out pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation and sleep mode, a wdt time-out gener- ates a device reset. the wdt can be permanently disabled by programming the con?uration bits wdtps1:wdtps0 as ' 00 ' (section 14.1). under normal operation, the wdt must be cleared on a regular interval. this time is less the minimum wdt over?w time. not clearing the wdt in this time frame will cause the wdt to over?w and reset the device. 14.3.1 wdt period the wdt has a nominal time-out period of 12 ms, (with postscaler = 1). the time-out periods vary with temper- ature, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a postscaler with a division ratio of up to 1:256 can be assigned to the wdt. thus, typical time-out periods up to 3.0 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and pre- vent it from timing out thus generating a device reset condition. the t o bit in the cpusta register will be cleared upon a wdt time-out. 14.3.2 clearing the wdt and postscaler the wdt and postscaler are cleared when: the device is in the reset state ? sleep instruction is executed ? clrwdt instruction is executed wake-up from sleep by an interrupt the wdt counter/postscaler will start counting on the ?st edge after the device exits the reset state. 14.3.3 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt postscaler) it may take several seconds before a wdt time-out occurs. the wdt and postscaler is the power-up timer during the power-on reset sequence. 14.3.4 wdt as normal timer when the wdt is selected as a normal timer, the clock source is the device clock. neither the wdt nor the postscaler are directly readable or writable. the over- ?w time is 65536 t osc cycles. on over?w, the t o bit is cleared (device is not reset). the clrwdt instruction can be used to set the t o bit. this allows the wdt to be a simple over?w timer. when in sleep, the wdt does not increment.
pic17c4x ds30412c-page 104 1996 microchip technology inc. figure 14-8: watchdog timer block diagram table 14-4: registers/bits associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note1) con? pm1 pm0 wdtps1 wdtps0 fosc1 fosc0 (note 2) (note 2) 06h, unbanked cpusta stkav glintd t o pd --11 11-- --11 qq-- legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the wdt. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. 2: this value will be as the device was programmed, or if unprogrammed, will read as all '1's. wdt wdt enable postscaler 4 - to - 1 mux wdtps1:wdtps0 on-chip rc wdt over?w oscillator (1) note 1: this oscillator is separate from the external rc oscillator on the osc1 pin.
1996 microchip technology inc. ds30412c-page 105 pic17c4x 14.4 p o wer - do wn mode (sleep) the power-down mode is entered by executing a sleep instruction. this clears the watchdog timer and postscaler (if enabled). the pd bit is cleared and the t o bit is set (in the cpusta register). in sleep mode, the oscillator driver is turned off. the i/o ports maintain their status (driving high, low, or hi-impedance). the mclr /v pp pin must be at a logic high level (v ihmc ). a wdt time-out reset does not drive the mclr /v pp pin low. 14.4.1 wake-up from sleep the device can wake up from sleep through one of the following events: a por reset external reset input on mclr /v pp pin wdt reset (if wdt was enabled) interrupt from ra0/int pin, rb port change, t0cki interrupt, or some peripheral interrupts the following peripheral interrupts can wake-up from sleep: capture1 interrupt capture2 interrupt usart synchronous slave transmit interrupt usart synchronous slave receive interrupt other peripherals can not generate interrupts since during sleep, no on-chip q clocks are present. any reset event will cause a device reset. any interrupt event is considered a continuation of program execu- tion. the t o and pd bits in the cpusta register can be used to determine the cause of device reset. the p d bit, which is set on power-up, is cleared when sleep is invoked. the t o bit is cleared if wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the glintd bit. if the glintd bit is set (disabled), the device continues execution at the instruction after the sleep instruction. if the glintd bit is clear (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt vector address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wake from sleep, regardless of the source of wake-up. 14.4.1.1 wake-up delay when the oscillator type is con?ured in xt or lf mode, the oscillator start-up timer (ost) is activated on wake-up. the ost will keep the device in reset for 1024t osc . this needs to be taken into account when considering the interrupt response time when coming out of sleep. note: if the global interrupts are disabled (glintd is set), but any interrupt source has both its interrupt enable bit and the cor- responding interrupt ?g bits set, the device will immediately wake-up from sleep. the t o bit is set, and the pd bit is cleared. figure 14-9: wake-up from sleep through interrupt q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout(4) int intf ?g glintd bit instr uction flo w pc instruction fetched instruction executed interrupt latency (2) pc pc+1 pc+2 0004h 0005h dummy cycle inst (pc) = sleep inst (pc+1) inst (pc-1) sleep tost(2) processor in sleep inst (pc+2) inst (pc+1) note 1: xt or lf oscillator mode assumed. 2: tost = 1024tosc (drawing not to scale). this delay will not be there for rc osc mode. 3: when glintd = 0 processor jumps to interrupt routine after wake-up. if glintd = 1, execution will continue in line. 4: clkout is not available in these osc modes, but shown here for timing reference. (ra0/int pin)
pic17c4x ds30412c-page 106 1996 microchip technology inc. 14.4.2 minimizing current consumption to minimize current consumption, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should be at v dd or v ss . the contributions from on-chip pull-ups on portb should also be con- sidered, and disabled when possible. 14.5 code pr otection the code in the program memory can be protected by selecting the microcontroller in code protected mode (pm2:pm0 = ' 000 '). in this mode, instructions that are in the on-chip pro- gram memory space, can continue to read or write the program memory. an instruction that is executed out- side of the internal program memory range will be inhib- ited from writing to or reading from program memory. if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for veri?ation purposes. note: pm2 does not exist on the pic17c42. to select code protected microcontroller mode, pm1:pm0 = ' 00 '. note: microchip does not recommend code pro- tecting windowed devices.
1996 microchip technology inc. ds30412c-page 107 pic17c4x 15.0 instruction set summary the pic17cxx instruction set consists of 58 instruc- tions. each instruction is a 16-bit word divided into an opcode and one or more operands. the opcode speci?s the instruction type, while the operand(s) fur- ther specify the operation of the instruction. the pic17cxx instruction set can be grouped into three types: byte-oriented bit-oriented literal and control operations. these formats are shown in figure 15-1. table 15-1 shows the ?ld descriptions for the opcodes. these descriptions are useful for under- standing the opcodes in table 15-2 and in each spe- ci? instruction descriptions. byte-oriented instructions , 'f' represents a ?e regis- ter designator and 'd' represents a destination designa- tor. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' = '0', the result is placed in the wreg register. if 'd' = '1', the result is placed in the ?e register speci?d by the instruction. bit-oriented instructions , 'b' represents a bit ?ld des- ignator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. literal and control operations , 'k' represents an 8- or 11-bit constant or literal value. the instruction set is highly orthogonal and is grouped into: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless: a conditional test is true the program counter is changed as a result of an instruction a table read or a table write instruction is exe- cuted (in this case, the execution takes two instruction cycles with the second cycle executed as a nop ) one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 25 mhz, the normal instruction execution time is 160 ns. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 320 ns. table 15-1: opcode field descriptions field description f register ?e address (00h to ffh) p peripheral register ?e address (00h to 1fh) i table pointer control i = '0' (do not change) i = '1' (increment after instruction execution) t table byte select t = '0' (perform operation on lower byte) t = '1' (perform operation on upper byte literal ?ld, constant data) wreg working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= '0' or '1') the assembler will generate code with x = '0'. it is the recommended form of use for compatibility with all microchip software tools. d destination select 0 = store result in wreg 1 = store result in ?e register f default is d = '1' u unused, encoded as '0' s destination select 0 = store result in ?e register f and in the wreg 1 = store result in ?e register f default is s = '1' label label name c,dc, z,ov alu status bits carry, digit carry, zero, over?w glintd global interrupt disable bit (cpusta<4>) tblptr table pointer (16-bit) tblat table latch (16-bit) consists of high byte (tblath) and low byte (tblatl) tblatl table latch low byte tblath table latch high byte tos top of stack pc program counter bsr bank select register wdt watchdog timer counter to time-out bit pd power-down bit dest destination either the wreg register or the speci- ?d register ?e location [ ] options ( ) contents assigned to < > register bit ?ld in the set of i talics user de?ed term (font is courier) this document was created with framemake r404
pic17c4x ds30412c-page 108 1996 microchip technology inc. table 15-2 lists the instructions recognized by the mpasm assembler. all instruction examples use the following format to rep- resent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. to represent a binary number: 0000 0100b where b signi?s a binary string. figure 15-1: general format for instructions note 1: any unused opcode is reserved. use of any reserved opcode may cause unex- pected operation. note 2: the shaded instructions are not available in the pic17c42 byte-oriented ?e register operations 15 9 8 7 0 d = 0 for destination wreg opcode d f (file #) d = 1 for destination f f = 8-bit ?e register address bit-oriented ?e register operations 15 11 10 8 7 0 opcode b (bit #) f (file #) b = 3-bit address f = 8-bit ?e register address literal and control operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations 15 13 12 8 7 0 opcode p (file #) f (file #) call and goto operations 15 13 12 0 opcode k (literal) k = 13-bit immediate value p = peripheral register ?e address f = 8-bit ?e register address 15.1 special functi on register s as sour ce/destination the pic17c4xs orthogonal instruction set allows read and write of all ?e registers, including special function registers. there are some special situations the user should be aware of: 15.1.1 alusta as destination if an instruction writes to alusta, the z, c, dc and ov bits may be set or cleared as a result of the instruction and overwrite the original data bits written. for exam- ple, executing clrf alusta will clear register alusta, and then set the z bit leaving 0000 0100b in the register. 15.1.2 pcl as source or destination read, write or read-modify-write on pcl may have the following results: read pc: pch pclath; pcl dest write pcl: pclath pch; 8-bit destination value pcl read-modify-write: pcl alu operand pclath pch; 8-bit result pcl where pch = program counter high byte (not an addressable register), pclath = program counter high holding latch, dest = destination, wreg or f. 15.1.3 bit manipulation all bit manipulation instructions are done by ?st read- ing the entire register, operating on the selected bit and writing the result back (read-modify-write). the user should keep this in mind when operating on special function registers, such as ports.
1996 microchip technology inc. ds30412c-page 109 pic17c4x 15.2 q cyc le activity each instruction cycle (tcy) is comprised of four q cycles (q1-q4). the q cycles provide the timing/desig- nation for the decode, read, execute, write etc., of each instruction cycle. the following diagram shows the relationship of the q cycles to the instruction cycle. the 4 q cycles that make up an instruction cycle (tcy) can be generalized as: q1: instruction decode cycle or forced nop q2: instruction read cycle or nop q3: instruction execute q4: instruction write cycle or nop each instruction will show the detailed q cycle opera- tion for the instruction. figure 15-2: q cycle activity q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 tcy1 tcy2 tcy3 tosc
pic17c4x ds30412c-page 110 1996 microchip technology inc. table 15-2: pic17cxx instruction set mnemonic, operands description cycles 16-bit opcode status affected notes msb lsb byte-oriented file register operations addwf f,d add wreg to f 1 0000 111d ffff ffff ov,c,dc,z addwfc f,d add wreg and carry bit to f 1 0001 000d ffff ffff ov,c,dc,z andwf f,d and wreg with f 1 0000 101d ffff ffff z clrf f,s clear f, or clear f and clear wreg 1 0010 100s ffff ffff none 3 comf f,d complement f 1 0001 001d ffff ffff z cpfseq f compare f with wreg, skip if f = wreg 1 (2) 0011 0001 ffff ffff none 6,8 cpfsgt f compare f with wreg, skip if f > wreg 1 (2) 0011 0010 ffff ffff none 2,6,8 cpfslt f compare f with wreg, skip if f < wreg 1 (2) 0011 0000 ffff ffff none 2,6,8 daw f,s decimal adjust wreg register 1 0010 111s ffff ffff c3 decf f,d decrement f 1 0000 011d ffff ffff ov,c,dc,z decfsz f,d decrement f, skip if 0 1 (2) 0001 011d ffff ffff none 6,8 dcfsnz f,d decrement f, skip if not 0 1 (2) 0010 011d ffff ffff none 6,8 incf f,d increment f 1 0001 010d ffff ffff ov,c,dc,z incfsz f,d increment f, skip if 0 1 (2) 0001 111d ffff ffff none 6,8 infsnz f,d increment f, skip if not 0 1 (2) 0010 010d ffff ffff none 6,8 iorwf f,d inclusive or wreg with f 1 0000 100d ffff ffff z movfp f,p move f to p 1 011p pppp ffff ffff none movpf p,f move p to f 1 010p pppp ffff ffff z movwf f move wreg to f 1 0000 0001 ffff ffff none mulwf f multiply wreg with f 1 0011 0100 ffff ffff none 9 negw f,s negate wreg 1 0010 110s ffff ffff ov,c,dc,z 1,3 nop no operation 1 0000 0000 0000 0000 none rlcf f,d rotate left f through carry 1 0001 101d ffff ffff c rlncf f,d rotate left f (no carry) 1 0010 001d ffff ffff none rrcf f,d rotate right f through carry 1 0001 100d ffff ffff c rrncf f,d rotate right f (no carry) 1 0010 000d ffff ffff none setf f,s set f 1 0010 101s ffff ffff none 3 subwf f,d subtract wreg from f 1 0000 010d ffff ffff ov,c,dc,z 1 subwfb f,d subtract wreg from f with borrow 1 0000 001d ffff ffff ov,c,dc,z 1 swapf f,d swap f 1 0001 110d ffff ffff none tablrd t,i,f table read 2 (3) 1010 10ti ffff ffff none 7 legend: refer to table 15-1 for opcode ?ld descriptions. note 1: 2s complement method. 2: unsigned arithmetic. 3: if s = '1', only the ?e is affected: if s = '0', both the wreg register and the ?e are affected; if only the working register (wreg) is required to be affected, then f = wreg must be speci?d. 4: during an lcall , the contents of pclath are loaded into the msb of the pc and kkkk kkkk is loaded into the lsb of the pc (pcl) 5: multiple cycle instruction for eprom programming when table pointer selects internal eprom. the instruc- tion is terminated by an interrupt event. when writing to external program memory, it is a two-cycle instruc- tion. 6: two-cycle instruction when condition is true, else single cycle instruction. 7: two-cycle instruction except for tablrd to pcl (program counter low byte) in which case it takes 3 cycles. 8: a ?kip means that instruction fetched during execution of current instruction is not executed, instead an nop is executed. 9: these instructions are not available on the pic17c42.
1996 microchip technology inc. ds30412c-page 111 pic17c4x tablwt t,i,f table write 2 1010 11ti ffff ffff none 5 tlrd t,f table latch read 1 1010 00tx ffff ffff none tlwt t,f table latch write 1 1010 01tx ffff ffff none tstfsz f test f, skip if 0 1 (2) 0011 0011 ffff ffff none 6,8 xorwf f,d exclusive or wreg with f 1 0000 110d ffff ffff z bit-oriented file register operations bcf f,b bit clear f 1 1000 1bbb ffff ffff none bsf f,b bit set f 1 1000 0bbb ffff ffff none btfsc f,b bit test, skip if clear 1 (2) 1001 1bbb ffff ffff none 6,8 btfss f,b bit test, skip if set 1 (2) 1001 0bbb ffff ffff none 6,8 btg f,b bit toggle f 1 0011 1bbb ffff ffff none literal and control operations addlw k add literal to wreg 1 1011 0001 kkkk kkkk ov,c,dc,z andlw k and literal with wreg 1 1011 0101 kkkk kkkk z call k subroutine call 2 111k kkkk kkkk kkkk none 7 clrwdt clear watchdog timer 1 0000 0000 0000 0100 t o ,pd goto k unconditional branch 2 110k kkkk kkkk kkkk none 7 iorlw k inclusive or literal with wreg 1 1011 0011 kkkk kkkk z lcall k long call 2 1011 0111 kkkk kkkk none 4,7 movlb k move literal to low nibble in bsr 1 1011 1000 uuuu kkkk none movlr k move literal to high nibble in bsr 1 1011 101x kkkk uuuu none 9 movlw k move literal to wreg 1 1011 0000 kkkk kkkk none mullw k multiply literal with wreg 1 1011 1100 kkkk kkkk none 9 retfie return from interrupt (and enable interrupts) 2 0000 0000 0000 0101 glintd 7 retlw k return literal to wreg 2 1011 0110 kkkk kkkk none 7 return return from subroutine 2 0000 0000 0000 0010 none 7 sleep enter sleep mode 1 0000 0000 0000 0011 t o , p d sublw k subtract wreg from literal 1 1011 0010 kkkk kkkk ov,c,dc,z xorlw k exclusive or literal with wreg 1 1011 0100 kkkk kkkk z table 15-2: pic17cxx instruction set (cont.d) mnemonic, operands description cycles 16-bit opcode status affected notes msb lsb legend: refer to table 15-1 for opcode ?ld descriptions. note 1: 2s complement method. 2: unsigned arithmetic. 3: if s = '1', only the ?e is affected: if s = '0', both the wreg register and the ?e are affected; if only the working register (wreg) is required to be affected, then f = wreg must be speci?d. 4: during an lcall , the contents of pclath are loaded into the msb of the pc and kkkk kkkk is loaded into the lsb of the pc (pcl) 5: multiple cycle instruction for eprom programming when table pointer selects internal eprom. the instruc- tion is terminated by an interrupt event. when writing to external program memory, it is a two-cycle instruc- tion. 6: two-cycle instruction when condition is true, else single cycle instruction. 7: two-cycle instruction except for tablrd to pcl (program counter low byte) in which case it takes 3 cycles. 8: a ?kip means that instruction fetched during execution of current instruction is not executed, instead an nop is executed. 9: these instructions are not available on the pic17c42.
pic17c4x ds30412c-page 112 1996 microchip technology inc. addlw add literal to wreg syntax: [ label ] addlw k operands: 0 k 255 operation: (wreg) + k (wreg) status affected: ov, c, dc, z encoding: 1011 0001 kkkk kkkk description: the contents of wreg are added to the 8-bit literal 'k' and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example : addlw 0x15 before instruction wreg = 0x10 after instruction wreg = 0x25 addwf add wreg to f syntax: [ label ] addwf f,d operands: 0 f 255 d ?[0,1] operation: (wreg) + (f) (dest) status affected: ov, c, dc, z encoding: 0000 111d ffff ffff description: add wreg to register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : addwf reg, 0 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0xd9 reg = 0xc2
1996 microchip technology inc. ds30412c-page 113 pic17c4x addwfc add wreg and carry bit to f syntax: [ label ] addwfc f,d operands: 0 f 255 d ?[0,1] operation: (wreg) + (f) + c (dest) status affected: ov, c, dc, z encoding: 0001 000d ffff ffff description: add wreg, the carry flag and data memory location 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : addwfc reg 0 before instruction carry bit = 1 reg = 0x02 wreg = 0x4d after instruction carry bit = 0 reg = 0x02 wreg = 0x50 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 k 255 operation: (wreg) .and. (k) (wreg) status affected: z encoding: 1011 0101 kkkk kkkk description: the contents of wreg are and?d with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example : andlw 0x5f before instruction wreg = 0xa3 after instruction wreg = 0x03
pic17c4x ds30412c-page 114 1996 microchip technology inc. andwf and wreg with f syntax: [ label ] andwf f,d operands: 0 f 255 d ?[0,1] operation: (wreg) .and. (f) (dest) status affected: z encoding: 0000 101d ffff ffff description: the contents of wreg are and?d with register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : andwf reg, 1 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0x17 reg = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 255 0 b 7 operation: 0 (f) status affected: none encoding: 1000 1bbb ffff ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
1996 microchip technology inc. ds30412c-page 115 pic17c4x bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 255 0 b 7 operation: 1 (f) status affected: none encoding: 1000 0bbb ffff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' example : bsf flag_reg, 7 before instruction flag_reg= 0x0a after instruction flag_reg= 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 255 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 1001 1bbb ffff ffff description: if bit 'b' in register ?' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruction fetched during the current instruction exe- cution is discarded, and a nop is exe- cuted instead, making this a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here false true btfsc : : flag,1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false)
pic17c4x ds30412c-page 116 1996 microchip technology inc. btfss bit test, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 1001 0bbb ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruction exe- cution, is discarded and an nop is exe- cuted instead, making this a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here false true btfss : : flag,1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) btg bit toggle f syntax: [ label ] btg f,b operands: 0 f 255 0 b < 7 operation: (f ) (f) status affected: none encoding: 0011 1bbb ffff ffff description: bit 'b' in data memory location 'f' is inverted. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' example : btg portc, 4 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65]
1996 microchip technology inc. ds30412c-page 117 pic17c4x call subroutine call syntax: [ label ] call k operands: 0 k 4095 operation: pc+ 1 tos, k pc<12:0>, k<12:8> pclath<4:0>; pc<15:13> pclath<7:5> status affected: none encoding: 111k kkkk kkkk kkkk description: subroutine call within 8k page. first, return address (pc+1) is pushed onto the stack. the 13-bit value is loaded into pc bits<12:0>. then the upper-eight bits of the pc are copied into pclath. call is a two-cycle instruction. see lcall for calls outside 8k memory space. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k'<7:0> execute nop forced nop nop execute nop example : here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f,s operands: 0 f 255 operation: 00h f, s [0,1] 00h dest status affected: none encoding: 0010 100s ffff ffff description: clears the contents of the speci?d reg- ister(s). s = 0: data memory location 'f' and wreg are cleared. s = 1: data memory location 'f' is cleared. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' and other speci?d register example : clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00
pic17c4x ds30412c-page 118 1996 microchip technology inc. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt postscaler, 1 t o 1 pd status affected: t o , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits t o and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register alusta execute nop example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 t o =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 255 d [0,1] operation: (dest) status affected: z encoding: 0001 001d ffff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' example : comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 wreg = 0xec (f)
1996 microchip technology inc. ds30412c-page 119 pic17c4x cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f operands: 0 f 255 operation: (f) ?(wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0011 0001 ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if 'f' = wreg then the fetched instruc- tion is discarded and an nop is exe- cuted instead making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here cpfseq reg nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg ? wreg; pc = address (nequal) cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f operands: 0 f 255 operation: (f) - ( wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0011 0010 ffff ffff description: compares the contents of data memory location 'f' to the contents of the wreg by performing an unsigned subtraction. if the contents of 'f' > the contents of wreg then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruc- tion. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg wreg; pc = address (ngreater)
pic17c4x ds30412c-page 120 1996 microchip technology inc. cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f operands: 0 f 255 operation: (f) ( wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0011 0000 ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if the contents of 'f' < the contents of wreg, then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruc- tion. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here cpfslt reg nless : less : before instruction pc = address (here) w= ? after instruction if reg < wreg; pc = address (less) if reg wreg; pc = address (nless) daw decimal adjust wreg register syntax: [ label ] daw f,s operands: 0 f 255 s [0,1] operation: if [wreg<3:0> >9] .or. [dc = 1] then wreg<3:0> + 6 f<3:0>, s<3:0>; else wreg<3:0> f<3:0>, s<3:0>; if [wreg<7:4> >9] .or. [c = 1] then wreg<7:4> + 6 f<7:4>, s<7:4> else wreg<7:4> f<7:4>, s<7:4> status affected: c encoding: 0010 111s ffff ffff description: daw adjusts the eight bit value in wreg resulting from the earlier addi- tion of two variables (each in packed bcd format) and produces a correct packed bcd result. s = 0: result is placed in data memory location 'f' and wreg. s = 1: result is placed in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' and other speci?d register example1 : daw reg1, 0 before instruction wreg = 0xa5 reg1 = ?? c=0 dc = 0 after instruction wreg = 0x05 reg1 = 0x05 c=1 dc = 0 e xample 2 : before instruction wreg = 0xce reg1 = ?? c=0 dc = 0 after instruction wreg = 0x24 reg1 = 0x24 c=1 dc = 0
1996 microchip technology inc. ds30412c-page 121 pic17c4x decf decrement f syntax: [ label ] decf f,d operands: 0 f 255 d [0,1] operation: (f) ?1 (dest) status affected: ov, c, dc, z encoding: 0000 011d ffff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 255 d [0,1] operation: (f) ?1 (dest); skip if result = 0 status affected: none encoding: 0001 011d ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead mak- ing it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here+1)
pic17c4x ds30412c-page 122 1996 microchip technology inc. dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f,d operands: 0 f 255 d [0,1] operation: (f) ?1 (dest); skip if not 0 status affected: none encoding: 0010 011d ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is not 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead mak- ing it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination if skip: q1 q2 q3 q4 forced nop nop execute nop example : here dcfsnz temp, 1 zero : nzero : before instruction temp_value = ? after instruction temp_value = temp_value - 1, if temp_value = 0; pc = address (zero ) if temp_value 0; pc = address (nzero) goto unconditional branch syntax: [ label ] goto k operands: 0 k 8191 operation: k pc<12:0>; k<12:8> pclath<4:0>, pc <15:13> pclath<7:5> status affected: none encoding: 110k kkkk kkkk kkkk description: goto allows an unconditional branch anywhere within an 8k page boundary. the thirteen bit immediate value is loaded into pc bits <12:0>. then the upper eight bits of pc are loaded into pclath. goto is always a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k'<7:0> execute nop forced nop nop execute nop example : goto there after instruction pc = address (there)
1996 microchip technology inc. ds30412c-page 123 pic17c4x incf increment f syntax: [ label ] incf f,d operands: 0 f 255 d [0,1] operation: (f) + 1 (dest) status affected: ov, c, dc, z encoding: 0001 010d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : incf cnt, 1 before instruction cnt = 0xff z=0 c=? after instruction cnt = 0x00 z=1 c=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 255 d [0,1] operation: (f) + 1 (dest) skip if result = 0 status affected: none encoding: 0001 111d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination if skip: q1 q2 q3 q4 forced nop nop execute nop example : here incfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero)
pic17c4x ds30412c-page 124 1996 microchip technology inc. infsnz increment f, skip if not 0 syntax: [ label ] infsnz f,d operands: 0 f 255 d [0,1] operation: (f) + 1 (dest), skip if not 0 status affected: none encoding: 0010 010d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is not 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination if skip: q1 q2 q3 q4 forced nop nop execute nop example : here infsnz reg, 1 zero nzero before instruction reg = reg after instruction reg = reg + 1 if reg = 1; pc = address (zero) if reg = 0; pc = address (nzero) iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 k 255 operation: (wreg) .or. (k) (wreg) status affected: z encoding: 1011 0011 kkkk kkkk description: the contents of wreg are or?d with the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example : iorlw 0x35 before instruction wreg = 0x9a after instruction wreg = 0xbf
1996 microchip technology inc. ds30412c-page 125 pic17c4x iorwf inclusive or wreg with f syntax: [ label ] iorwf f,d operands: 0 f 255 d [0,1] operation: (wreg) .or. (f) (dest) status affected: z encoding: 0000 100d ffff ffff description: inclusive or wreg with register 'f'. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in regis- ter 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : iorwf result, 0 before instruction result = 0x13 wreg = 0x91 after instruction result = 0x13 wreg = 0x93 lcall long call syntax: [ label ] lcall k operands: 0 k 255 operation: pc + 1 tos; k pcl, (pclath) pch status affected: none encoding: 1011 0111 kkkk kkkk description: lcall allows an unconditional subrou- tine call to anywhere within the 64k pro- gram memory space. first, the return address (pc + 1) is pushed onto the stack. a 16-bit desti- nation address is then loaded into the program counter. the lower 8-bits of the destination address is embedded in the instruction. the upper 8-bits of pc is loaded from pc high holding latch, pclath. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write register pcl forced nop nop execute nop example : movlw high(subroutine) movpf wreg, pclath lcall low(subroutine) before instruction subroutine = 16-bit address pc = ? after instruction pc = address (subroutine)
pic17c4x ds30412c-page 126 1996 microchip technology inc. movfp move f to p syntax: [ label ] movfp f,p operands: 0 f 255 0 p 31 operation: (f) (p) status affected: none encoding: 011p pppp ffff ffff description: move data from data memory location 'f' to data memory location 'p'. location 'f' can be anywhere in the 256 word data space (00h to ffh) while 'p' can be 00h to 1fh. either ?' or 'f' can be wreg (a useful special situation). movfp is particularly useful for transfer- ring a data memory location to a periph- eral register (such as the transmit buffer or an i/o port). both 'f' and 'p' can be indirectly addressed. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'p' example : movfp reg1, reg2 before instruction reg1 = 0x33, reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 15 operation: k (bsr<3:0>) status affected: none encoding: 1011 1000 uuuu kkkk description: the four bit literal 'k' is loaded in the bank select register (bsr). only the low 4-bits of the bank select register are affected. the upper half of the bsr is unchanged. the assembler will encode the ? ?lds as '0'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'u:k' execute write literal 'k' to bsr<3:0> example : movlb 0x5 before instruction bsr register = 0x22 after instruction bsr register = 0x25 note: for the pic17c42, only the low four bits of the bsr register are physically imple- mented. the upper nibble is read as '0'.
1996 microchip technology inc. ds30412c-page 127 pic17c4x movlr move literal to high nibble in bsr syntax: [ label ] movlr k operands: 0 k 15 operation: k (bsr<7:4>) status affected: none encoding: 1011 101x kkkk uuuu description: the 4-bit literal 'k' is loaded into the most signi?ant 4-bits of the bank select register (bsr). only the high 4-bits of the bank select register are affected. the lower half of the bsr is unchanged. the assembler will encode the ? ?lds as 0. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k:u' execute write literal 'k' to bsr<7:4> example : movlr 5 before instruction bsr register = 0x22 after instruction bsr register = 0x52 note: this instruction is not available in the pic17c42 device. movlw move literal to wreg syntax: [ label ] movlw k operands: 0 k 255 operation: k (wreg) status affected: none encoding: 1011 0000 kkkk kkkk description: the eight bit literal 'k' is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example : movlw 0x5a after instruction wreg = 0x5a
pic17c4x ds30412c-page 128 1996 microchip technology inc. movpf move p to f syntax: [ label ] movpf p,f operands: 0 f 255 0 p 31 operation: (p) (f) status affected: z encoding: 010p pppp ffff ffff description: move data from data memory location 'p' to data memory location 'f'. location 'f' can be anywhere in the 256 byte data space (00h to ffh) while 'p' can be 00h to 1fh. either 'p' or 'f' can be wreg (a useful special situation). movpf is particularly useful for transfer- ring a peripheral register (e.g. the timer or an i/o port) to a data memory loca- tion. both 'f' and 'p' can be indirectly addressed. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'p' execute write register 'f' example : movpf reg1, reg2 before instruction reg1 = 0x11 reg2 = 0x33 after instruction reg1 = 0x11 reg2 = 0x11 movwf move wreg to f syntax: [ label ] movwf f operands: 0 f 255 operation: (wreg) (f) status affected: none encoding: 0000 0001 ffff ffff description: move data from wreg to register 'f'. location 'f' can be anywhere in the 256 word data space. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' example : movwf reg before instruction wreg = 0x4f reg = 0xff after instruction wreg = 0x4f reg = 0x4f
1996 microchip technology inc. ds30412c-page 129 pic17c4x mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 k 255 operation: (k x wreg) prodh:prodl status affected: none encoding: 1011 1100 kkkk kkkk description: an unsigned multiplication is carried out between the contents of wreg and the 8-bit literal 'k'. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status ?gs are affected. note that neither over?w nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write registers prodh: prodl example : mullw 0xc4 before instruction wreg = 0xe2 prodh = ? prodl = ? after instruction wreg = 0xc4 prodh = 0xad prodl = 0x08 note: this instruction is not available in the pic17c42 device. mulwf multiply wreg with f syntax: [ label ] mulwf f operands: 0 f 255 operation: (wreg x f) prodh:prodl status affected: none encoding: 0011 0100 ffff ffff description: an unsigned multiplication is carried out between the contents of wreg and the register ?e location 'f'. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and 'f' are unchanged. none of the status ?gs are affected. note that neither over?w nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write registers prodh: prodl example : mulwf reg before instruction wreg = 0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction wreg = 0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94 note: this instruction is not available in the pic17c42 device.
pic17c4x ds30412c-page 130 1996 microchip technology inc. negw negate w syntax: [ label ] negw f,s operands: 0 f 255 s [0,1] operation: wreg + 1 (f); wreg + 1 s status affected: ov, c, dc, z encoding: 0010 110s ffff ffff description: wreg is negated using twos comple- ment. if 's' is 0 the result is placed in wreg and data memory location 'f'. if 's' is 1 the result is placed only in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' and other speci?d register example : negw reg,0 before instruction wreg = 0011 1010 [0x3a], reg = 1010 1011 [0xab] after instruction wreg = 1100 0111 [0xc6] reg = 1100 0111 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 0000 description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode nop execute nop example : none.
1996 microchip technology inc. ds30412c-page 131 pic17c4x retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos (pc); 0 glintd; pclath is unchanged. status affected: glintd encoding: 0000 0000 0000 0101 description: return from interrupt. stack is pop?d and top of stack (tos) is loaded in the pc. interrupts are enabled by clearing the glintd bit. glintd is the global interrupt disable bit (cpusta<4>). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register t0sta execute nop forced nop nop execute nop example : retfie after interrupt pc = tos glintd = 0 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 k 255 operation: k (wreg); tos (pc); pclath is unchanged status affected: none encoding: 1011 0110 kkkk kkkk description: wreg is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg forced nop nop execute nop example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pc ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 0x07 after instruction wreg = value of k7
pic17c4x ds30412c-page 132 1996 microchip technology inc. return return from subroutine syntax: [ label ] return operands: none operation: tos pc; status affected: none encoding: 0000 0000 0000 0010 description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register pcl* execute nop forced nop nop execute nop * remember reading pcl causes pclath to be updated. this will be the high address of where the return instruc- tion is located. example : return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f,d operands: 0 f 255 d [0,1] operation: f d; f<7> c; c d<0> status affected: c encoding: 0001 101d ffff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : rlcf reg,0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 wreg = 1100 1100 c=1 c register f
1996 microchip technology inc. ds30412c-page 133 pic17c4x rlncf rotate left f (no carry) syntax: [ label ] rlncf f,d operands: 0 f 255 d [0,1] operation: f d; f<7> d<0> status affected: none encoding: 0010 001d ffff ffff description: the contents of register 'f' are rotated one bit to the left. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : rlncf reg, 1 before instruction c=0 reg = 1110 1011 after instruction c= reg = 1101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f,d operands: 0 f 255 d [0,1] operation: f d; f<0> c; c d<7> status affected: c encoding: 0001 100d ffff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : rrcf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 wreg = 0111 0011 c= 0 c register f
pic17c4x ds30412c-page 134 1996 microchip technology inc. rrncf rotate right f (no carry) syntax: [ label ] rrncf f,d operands: 0 f 255 d [0,1] operation: f d; f<0> d<7> status affected: none encoding: 0010 000d ffff ffff description: the contents of register 'f' are rotated one bit to the right. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example 1 : rrncf reg, 1 before instruction wreg = ? reg = 1101 0111 after instruction wreg = 0 reg = 1110 1011 example 2 : rrncf reg, 0 before instruction wreg = ? reg = 1101 0111 after instruction wreg = 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f,s operands: 0 f 255 s [0,1] operation: ffh f; ffh d status affected: none encoding: 0010 101s ffff ffff description: if 's' is 0, both the data memory location 'f' and wreg are set to ffh. if 's' is 1 only the data memory location 'f' is set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register 'f' and other speci?d register example1 : setf reg, 0 before instruction reg = 0xda wreg = 0x05 after instruction reg = 0xff wreg = 0xff example2 : setf reg, 1 before instruction reg = 0xda wreg = 0x05 after instruction reg = 0xff wreg = 0x05
1996 microchip technology inc. ds30412c-page 135 pic17c4x sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt postscaler; 1 t o ; 0 pd status affected: t o , pd encoding: 0000 0000 0000 0011 description: the power down status bit (pd ) is cleared. the time-out status bit (t o ) is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register pclath execute nop example : sleep before instruction t o =? pd =? after instruction t o =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared sublw subtract wreg from literal syntax: [ label ] sublw k operands: 0 ? k ? 255 operation: k ?(wreg) ( wreg) status affected: ov, c, dc, z encoding: 1011 0010 kkkk kkkk description: wreg is subtracted from the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example 1 : sublw 0x02 before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 example 2 : before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 example 3 : before instruction wreg = 3 c=? after instruction wreg = ff ; (2s complement) c = 0 ; result is negative z=1
pic17c4x ds30412c-page 136 1996 microchip technology inc. subwf subtract wreg from f syntax: [ label ] subwf f,d operands: 0 ? f ? 255 d [0,1] operation: (f) ?(w) ( dest) status affected: ov, c, dc, z encoding: 0000 010d ffff ffff description: subtract wreg from register 'f' (2s complement method). if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example 1 : subwf reg1, 1 before instruction reg1 = 3 wreg = 2 c=? after instruction reg1 = 1 wreg = 2 c = 1 ; result is positive z=0 example 2 : before instruction reg1 = 2 wreg = 2 c=? after instruction reg1 = 0 wreg = 2 c = 1 ; result is zero z=1 example 3 : before instruction reg1 = 1 wreg = 2 c=? after instruction reg1 = ff wreg = 2 c = 0 ; result is negative z=0 subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f,d operands: 0 f 255 d [0,1] operation: (f) ?(w) ?c ( dest) status affected: ov, c, dc, z encoding: 0000 001d ffff ffff description: subtract wreg and the carry ?g (borrow) from register 'f' (2s comple- ment method). if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example 1 : subwfb reg1, 1 before instruction reg1 = 0x19 ( 0001 1001 ) wreg = 0x0d ( 0000 1101 ) c=1 after instruction reg1 = 0x0c ( 0000 1011 ) wreg = 0x0d ( 0000 1101 ) c = 1 ; result is positive z=0 example2 : subwfb reg1,0 before instruction reg1 = 0x1b ( 0001 1011 ) wreg = 0x1a ( 0001 1010 ) c=0 after instruction reg1 = 0x1b ( 0001 1011 ) wreg = 0x00 c = 1 ; result is zero z=1 example3 : subwfb reg1,1 before instruction reg1 = 0x03 ( 0000 0011 ) wreg = 0x0e ( 0000 1101 ) c=1 after instruction reg1 = 0xf5 ( 1111 0100 ) [2s comp] wreg = 0x0e ( 0000 1101 ) c = 0 ; result is negative z=0
1996 microchip technology inc. ds30412c-page 137 pic17c4x swapf swap f syntax: [ label ] swapf f,d operands: 0 f 255 d [0,1] operation: f<3:0> dest<7:4>; f<7:4> dest<3:0> status affected: none encoding: 0001 110d ffff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : swapf reg, 0 before instruction reg = 0x53 after instruction reg = 0x35 tablrd table read syntax: [ label ] tablrd t,i,f operands: 0 f 255 i ? [0,1] t ? [0,1] operation: if t = 1, tblath f; if t = 0, tblatl f; prog mem (tblptr) tblat; if i = 1, tblptr + 1 tblptr status affected: none encoding: 1010 10ti ffff ffff description: 1. a byte of the table latch (tblat) is moved to register ?e 'f'. if t = 0: the high byte is moved; if t = 1: the low byte is moved 2. then the contents of the program memory location pointed to by the 16-bit table pointer (tblptr) is loaded into the 16-bit table latch (tblat). 3. if i = 1: tblptr is incremented; if i = 0: tblptr is not incremented words: 1 cycles: 2 (3 cycle if f = pcl) q cycle activity: q1 q2 q3 q4 decode read register tblath or tblatl execute write register 'f'
pic17c4x ds30412c-page 138 1996 microchip technology inc. tablrd table read example1 : tablrd 1, 1, reg ; before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0x1234 after instruction (table write completion) reg = 0xaa tblath = 0x12 tblatl = 0x34 tblptr = 0xa357 memory(tblptr) = 0x5678 example2 : tablrd 0, 0, reg ; before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0x1234 after instruction (table write completion) reg = 0x55 tblath = 0x12 tblatl = 0x34 tblptr = 0xa356 memory(tblptr) = 0x1234 tablwt table write syntax: [ label ] tablwt t,i,f operands: 0 f 255 i ? [0,1] t ? [0,1] operation: if t = 0, f tblatl; if t = 1, f tblath; tblat prog mem (tblptr); if i = 1, tblptr + 1 tblptr status affected: none encoding: 1010 11ti ffff ffff description: 1. load value in ? into 16-bit table latch (tblat) if t = 0: load into low byte; if t = 1: load into high byte 2. the contents of tblat is written to the program memory location pointed to by tblptr if tblptr points to external program memory location, then the instruction takes two-cycle if tblptr points to an internal eprom location, then the instruction is terminated when an interrupt is received. note: the mclr /v pp pin must be at the programming voltage for successful programming of internal memory. if mclr /v pp = v dd the programming sequence of internal memory will be executed, but will not be successful (although the internal memory location may be disturbed) 3. the tblptr can be automati- cally incremented if i = 0; tblptr is not incremented if i = 1; tblptr is incremented words: 1 cycles: 2 (many if write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register tblath or tblatl
1996 microchip technology inc. ds30412c-page 139 pic17c4x tablwt table write example1 : tablwt 0, 1, reg before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0xffff after instruction (table write completion) reg = 0x53 tblath = 0x53 tblatl = 0x55 tblptr = 0xa357 memory(tblptr - 1) = 0x5355 example 2 : tablwt 1, 0, reg before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0xffff after instruction (table write completion) reg = 0x53 tblath = 0xaa tblatl = 0x53 tblptr = 0xa356 memory(tblptr) = 0xaa53 program memory 16 bits 15 0 tblptr tblat data memory 8 bits 15 8 70 tlrd table latch read syntax: [ label ] tlrd t,f operands: 0 f 255 t ? [0,1] operation: if t = 0, tblatl f; if t = 1, tblath f status affected: none encoding: 1010 00tx ffff ffff description: read data from 16-bit table latch (tblat) into ?e register 'f'. table latch is unaffected. if t = 1; high byte is read if t = 0; low byte is read this instruction is used in conjunction with tablrd to transfer data from pro- gram memory to data memory. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register tblath or tblatl execute write register 'f' example : tlrd t, ram before instruction t=0 ram = ? tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) after instruction ram = 0xaf tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) before instruction t=1 ram = ? tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) after instruction ram = 0x00 tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) program memory 16 bits 15 0 tblptr tblat data memory 8 bits 15 8 70
pic17c4x ds30412c-page 140 1996 microchip technology inc. tlwt table latch write syntax: [ label ] tlwt t,f operands: 0 f 255 t ? [0,1] operation: if t = 0, f tblatl; if t = 1, f tblath status affected: none encoding: 1010 01tx ffff ffff description: data from ?e register 'f' is written into the 16-bit table latch (tblat). if t = 1; high byte is written if t = 0; low byte is written this instruction is used in conjunction with tablwt to transfer data from data memory to program memory. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write register tblath or tblatl example : tlwt t, ram before instruction t=0 ram = 0xb7 tblat = 0x0000 (tblath = 0x00) (tblatl = 0x00) after instruction ram = 0xb7 tblat = 0x00b7 (tblath = 0x00) (tblatl = 0xb7) before instruction t=1 ram = 0xb7 tblat = 0x0000 (tblath = 0x00) (tblatl = 0x00) after instruction ram = 0xb7 tblat = 0xb700 (tblath = 0xb7) (tblatl = 0x00) tstfsz test f, skip if 0 syntax: [ label ] tstfsz f operands: 0 f 255 operation: skip if f = 0 status affected: none encoding: 0011 0011 ffff ffff description: if 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and an nop is executed making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' execute nop if skip: q1 q2 q3 q4 forced nop nop execute nop example : here tstfsz cnt nzero : zero : before instruction pc = address( here ) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero)
1996 microchip technology inc. ds30412c-page 141 pic17c4x xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 ? k ? 255 operation: (wreg) .xor. k ( wreg) status affected: z encoding: 1011 0100 kkkk kkkk description: the contents of wreg are xor?d with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' execute write to wreg example : xorlw 0xaf before instruction wreg = 0xb5 after instruction wreg = 0x1a xorwf exclusive or wreg with f syntax: [ label ] xorwf f,d operands: 0 f 255 d [0,1] operation: (wreg) .xor. (f) ( dest) status affected: z encoding: 0000 110d ffff ffff description: exclusive or the contents of wreg with register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in the register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' execute write to destination example : xorwf reg, 1 before instruction reg = 0xaf wreg = 0xb5 after instruction reg = 0x1a wreg = 0xb5
pic17c4x ds30412c-page 142 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 143 pic17c4x 16.0 development support 16.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster/picmaster ce real-time in-circuit emulator icepic low-cost pic16c5x and pic16cxxx in-circuit emulator pro mate ii universal programmer picstart plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab-sim software simulator mplab-c (c compiler) fuzzy logic development system (fuzzytech - mp) 16.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic12c5xx, pic14000, pic16c5x, pic16cxxx and pic17cxx families. picmaster is supplied with the mplab integrated development environment (ide), which allows editing, ?ake and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and higher) machine platform and microsoft windows 3.x environment were chosen to best make these fea- tures available to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 16.3 i cepic: lo w-cost pic16cxxx in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at through pentium based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 16.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic16c5x, pic16cxxx, pic17cxx and pic14000 devices. it can also set con?uration and code-protect bits in this mode. 16.5 p icst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12c5xx, pic14000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket. this document was created with framemake r404
pic17c4x ds30412c-page 144 1996 microchip technology inc. 16.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 16.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 16.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?m- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. the picdem-3 pro- vides an additional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to con- struct a hardware demultiplexer for the lcd signals. picdem-3 will be available in the 3rd quarter of 1996. 16.9 mplab integrated de velopment en vir onment softwar e the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 16.10 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers.
1996 microchip technology inc. ds30412c-page 145 pic17c4x mpasm allow full symbolic debugging from the microchip universal emulator system (picmaster). mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. 16.11 s oftware sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 16.12 c compiler ( mplab-c) the mplab-c code development system is a complete ? compiler and integrated development environment for microchips pic16/17 family of micro- controllers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display (picmaster emulator software versions 1.13 and later). 16.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab demon- stration board for hands-on experience with fuzzy logic systems implementation. 16.14 mp-drivew a y ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 16.15 seev al ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials and secure serials. the total endurance disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 16.16 t ruegaug e intellig ent batter y mana g ement the truegauge development tool supports system development with the mta11200b truegauge intelli- gent battery management ic. system design veri?a- tion can be accomplished before hardware prototypes are built. user interface is graphically-oriented and measured data can be saved in a ?e for exporting to microsoft excel. 16.17 k ee l oq ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic17c4x ds30412c-page 146 1996 microchip technology inc. table 16-1: development tools from microchip product ** mplab integrated development environment mplab c compiler mp-driveway applications code generator fuzzytech -mp explorer/edition fuzzy logic dev. tool *** picmaster / picmaster-ce in-circuit emulator icepic low-cost in-circuit emulator ****pro mate ii universal microchip programmer picstart lite ultra low-cost dev. kit picstart plus low-cost universal dev. kit pic12c508, 509 sw007002 sw006005 em167015/ em167101 dv007003 dv003001 pic14000 sw007002 sw006005 em147001/ em147101 dv007003 dv003001 pic16c52, 54, 54a, 55, 56, 57, 58a sw007002 sw006005 sw006006 dv005001/ dv005002 em167015/ em167101 em167201 dv007003 dv162003 dv003001 pic16c554, 556, 558 sw007002 sw006005 dv005001/ dv005002 em167033/ em167113 ? dv007003 dv003001 pic16c61 sw007002 sw006005 sw006006 dv005001/ dv005002 em167021/ n/a em167205 dv007003 dv162003 dv003001 pic16c62, 62a, 64, 64a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167203 dv007003 dv162002 dv003001 pic16c620, 621, 622 sw007002 sw006005 sw006006 dv005001/ dv005002 em167023/ em167109 em167202 dv007003 dv162003 dv003001 pic16c63, 65, 65a, 73, 73a, 74, 74a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167204 dv007003 dv162002 dv003001 pic16c642, 662* sw007002 sw006005 em167035/ em167105 ? dv007003 dv162002 dv003001 pic16c71 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 em167205 dv007003 dv162003 dv003001 pic16c710, 711 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 dv007003 dv162003 dv003001 pic16c72 sw007002 sw006005 sw006006 em167025/ em167103 dv007003 dv162002 dv003001 pic16f83 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 em167206 dv007003 dv162003 dv003001 pic16f84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c923, 924* sw007002 sw006005 sw006006 dv005001/ dv005002 em167031/ em167111 dv007003 dv003001 pic17c42, 42a, 43, 44 sw007002 sw006005 sw006006 dv005001/ dv005002 em177007/ em177107 dv007003 dv003001 *contact microchip technology for availability date **mplab integrated development environment includes mplab-sim simulator and mpasm assembler ***all picmaster and picmaster-ce ordering part numbers above include pro mate ii programmer ****pro mate socket modules are ordered separately. see development systems ordering guide for specic ordering part numbers product truegauge development kit seeval designers kit hopping code security programmer kit hopping code security eval/demo kit all 2 wire and 3 wire serial eeprom's n/a dv243001 n/a n/a mta11200b dv114001 n/a n/a n/a hcs200, 300, 301 * n/a n/a pg306001 dm303001
1996 microchip technology inc. ds30412c-page 147 pic17c4x applicable devices 42 r42 42a 43 r43 44 17.0 pic17c42 electrical characteristics absolute maximum ratings ? ambient temperature under bias..................................................................................................................-55 to +125?c storage temperature ............................................................................................................................... -65?c to +150?c voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) ..........................................................................................-0.6v to +14v voltage on ra2 and ra3 with respect to v ss ..............................................................................................-0.6v to +12v voltage on all other pins with respect to v ss ..................................................................................... -0.6v to v dd + 0.6v total power dissipation (note 1).................................................................................................................................1.0w maximum current out of v ss pin(s) - total .............................................................................................................250 ma maximum current into v dd pin(s) - total ................................................................................................................200 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin (except ra2 and ra3)......................................................................35 ma maximum output current sunk by ra2 or ra3 pins .................................................................................................60 ma maximum output current sourced by any i/o pin .....................................................................................................20 ma maximum current sunk by porta and portb (combined)..................................................................................150 ma maximum current sourced by porta and portb (combined).............................................................................100 ma maximum current sunk by portc, portd and porte (combined)...................................................................150 ma maximum current sourced by portc, portd and porte (combined)..............................................................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a "low" level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic17c4x ds30412c-page 148 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 table 17-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic17c42-16 pic17c42-25 rc v dd : 4.5v to 5.5v i dd : 6 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 6 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 4 mhz max. xt v dd : 4.5v to 5.5v i dd : 24 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 16 mhz max. v dd : 4.5v to 5.5v i dd : 38 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 25 mhz max. ec v dd : 4.5v to 5.5v i dd : 24 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 16 mhz max. v dd : 4.5v to 5.5v i dd : 38 ma max. i pd : 5 m a max. at 5.5v (wdt disabled) freq: 25 mhz max. lf v dd : 4.5v to 5.5v i dd : 150 m a max. at 32 khz (wdt enabled) i pd : 5 m a max. at 5.5v (wdt disabled) freq: 2 mhz max. v dd : 4.5v to 5.5v i dd : 150 m a max. at 32 khz (wdt enabled) i pd : 5 m a max. at 5.5v (wdt disabled) freq: 2 mhz max.
1996 microchip technology inc. ds30412c-page 149 pic17c4x applicable devices 42 r42 42a 43 r43 44 17.1 dc characteristics: pic17c42-16 (commercial, industrial) pic17c42-25 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial parameter no. sym characteristic min typ? max units conditions d001 v dd supply voltage 4.5 5.5 v d002 v dr ram data retention voltage (note 1) 1.5 * v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.060* mv/ms see section on power-on reset for details d010 d011 d012 d013 d014 i dd supply current (note 2) 3 6 11 19 95 6 12 * 24 * 38 150 ma ma ma ma m a f osc = 4 mhz (note 4) f osc = 8 mhz f osc = 16 mhz f osc = 25 mhz f osc = 32 khz wdt enabled (ec osc con?uration) d020 d021 i pd power-down current (note 3) 10 < 1 40 5 m a m a v dd = 5.5v, wdt enabled v dd = 5.5v, wdt disabled * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd or v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. current consumed from the oscillator and i/os driving external capacitive or resistive loads need to be con- sidered. for the rc oscillator, the current through the external pull-up resistor (r) can be estimated as: v dd / (2 r). for capacitive loads, the current can be estimated (for an individual i/o pin) as (c l v dd ) f c l = total capacitive load on the i/o pin; f = average frequency on the i/o pin switches. the capacitive currents are most signi?ant when the device is con?ured for external execution (includes extended microcontroller mode). 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm.
pic17c4x ds30412c-page 150 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 17.2 dc characteristics: pic17c42-16 (commercial, industrial) pic17c42-25 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 17.1 parameter no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss 0.8 v d031 with schmitt trigger buffer v ss 0.2v dd v d032 mclr , osc1 (in ec and rc mode) vss 0.2v dd v note1 d033 osc1 (in xt, and lf mode) 0.5v dd ? input high voltage v ih i/o ports d040 with ttl buffer 2.0 v dd v d041 with schmitt trigger buffer 0.8v dd ? dd v d042 mclr 0.8v dd ? dd v note1 d043 osc1 (xt, and lf mode) 0.5v dd ? d050 v hys hysteresis of schmitt trigger inputs 0.15v dd * v input leakage current (notes 2, 3) d060 i il i/o ports (except ra2, ra3) 1 m a vss ? v pin ? v dd , i/o pin at hi-impedance portb weak pull-ups dis- abled d061 mclr 2 m av pin = vss or v pin = v dd d062 ra2, ra3 2 m a vss ? v ra 2, v ra 3 12v d063 osc1, test 1 m a vss ? v pin ? v dd d064 mclr 10 m av mclr = v pp = 12v (when not programming) d070 i purb portb weak pull-up current 60 200 400 m a v pin = v ss , rbpu = 0 * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. ?? design guidance to attain the ac timing speci?ations. these loads are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: these speci?ations are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming speci?ations can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /vpp pin may be kept in this range at times other than programming, but this is not recommended. 6: for ttl buffers, the better of the two speci?ations may be used.
1996 microchip technology inc. ds30412c-page 151 pic17c4x applicable devices 42 r42 42a 43 r43 44 output low voltage d080 d081 v ol i/o ports (except ra2 and ra3) with ttl buffer 0.1v dd 0.4 v v i ol = 4 ma i ol = 6 ma, v dd = 4.5v note 6 d082 ra2 and ra3 3.0 v i ol = 60.0 ma, v dd = 5.5v d083 osc2/clkout (rc and ec osc modes) 0.4 v i ol = 2 ma, v dd = 4.5v output high voltage (note 3) d090 d091 v oh i/o ports (except ra2 and ra3) with ttl buffer 0.9v dd 2.4 v v i oh = -2 ma i oh = -6.0 ma, v dd = 4.5v note 6 d092 ra2 and ra3 12 v pulled-up to externally applied voltage d093 osc2/clkout (rc and ec osc modes) 2.4 v i oh = -5 ma, v dd = 4.5v capacitive loading specs on output pins d100 c osc2 osc2 pin 25 ?? pf in ec or rc osc modes when osc2 pin is outputting clkout. external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) 50 ?? pf d102 c ad system interface bus (portc, portd and porte) 100 ?? pf in microprocessor or extended microcontroller mode dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 17.1 parameter no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. ?? design guidance to attain the ac timing speci?ations. these loads are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: these speci?ations are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming speci?ations can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /vpp pin may be kept in this range at times other than programming, but this is not recommended. 6: for ttl buffers, the better of the two speci?ations may be used.
pic17c4x ds30412c-page 152 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +40?c operating voltage v dd range as described in section 17.1 parameter no. sym characteristic min typ? max units conditions internal program memory programming specs (note 4) d110 d111 d112 d113 d114 v pp v ddp i pp i ddp t prog voltage on mclr /v pp pin supply voltage during programming current into mclr /v pp pin supply current during programming programming pulse width 12.75 4.75 10 5.0 25 100 13.25 5.25 50 30 1000 v v ma ma m s note 5 terminated via internal/exter- nal interrupt or a reset * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: these speci?ations are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming speci?ations can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two speci?ations may be used. note: when using the table write for internal programming, the device temperature must be less than 40?c.
1996 microchip technology inc. ds30412c-page 153 pic17c4x applicable devices 42 r42 42a 43 r43 44 17.3 timing p arameter symbology the timing parameter symbols have been created using one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase symbols (pp) and their meanings: pp ad address/data ost oscillator start-up timer al ale pwrt power-up timer cc capture1 and capture2 rb portb ck clkout or clock rd rd dt data in rw rd or wr in int pin t0 t0cki io i/o port t123 tclk12 and tclk3 mc mclr wdt watchdog timer oe oe wr wr os osc1 uppercase symbols and their meanings: s d driven l low e edge p period f fall r rise h high v valid i invalid (hi-impedance) z hi-impedance
pic17c4x ds30412c-page 154 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 17-1: parameter measurement information all timings are measure between high and low measurement points as indicated in the ?ures below. 0.9v dd 0.1v dd rise time fall time v oh = 0.7v dd v dd /2 v ol = 0.3v dd data out valid data out invalid output hi-impedance output driven 0.25v 0.25v 0.25v 0.25v output level conditions portc, d and e pins all other input pins v ih = 2.4v v il = 0.4v data in valid data in invalid v ih = 0.9v dd v il = 0.1v dd data in valid data in invalid input level conditions load conditions c l load condition 1 load condition 2 r l pin v ss v dd /2 pin c l v ss r l = 464 c l 50 pf
1996 microchip technology inc. ds30412c-page 155 pic17c4x applicable devices 42 r42 42a 43 r43 44 17.4 timing dia grams and speci cations figure 17-2: external clock timing table 17-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc dc 16 25 mhz mhz ec osc mode - pic17c42-16 - pic17c42-25 oscillator frequency (note 1) dc 1 1 dc 4 16 25 2 mhz mhz mhz mhz rc osc mode xt osc mode - pic17c42-16 - pic17c42-25 lf osc mode 1 tosc external clkin period (note 1) 62.5 40 ns ns ec osc mode - pic17c42-16 - pic17c42-25 oscillator period (note 1) 250 62.5 40 500 1,000 1,000 ns ns ns ns rc osc mode xt osc mode - pic17c42-16 - pic17c42-25 lf osc mode 2t cy instruction cycle time (note 1) 160 4/fosc dc ns 3 tosl, tosh clock in (osc1) high or low time 10 ns ec oscillator 4 tosr, tosf clock in (osc1) rise or fall time 5 ns ec oscillator ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in unstable oscillator operation and/or higher than expected current consump- tion. all devices are tested to operate at ?in. values with an external clock applied to the osc1 pin. when an external clock input is used, the ?ax. cycle time limit is ?c (no clock) for all devices. osc1 osc2 ? q4 q1 q2 q3 q4 q1 13344 2 ? in ec and rc modes only.
pic17c4x ds30412c-page 156 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 17-3: clkout and i/o timing table 17-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 to clkout 15 30 ns note 1 11 tosh2ckh osc1 to clkout 15 30 ns note 1 12 tckr clkout rise time 5 15 ns note 1 13 tckf clkout fall time 5 15 ns note 1 14 tckh2iov clkout to port out valid 0.5t cy + 20 ns note 1 15 tiov2ckh port in valid before clkout 0.25t cy + 25 ns note 1 16 tckh2ioi port in hold after clkout 0 ns note 1 17 tosh2iov osc1 (q1 cycle) to port out valid 100 ns 20 tior port output rise time 10 35 ns 21 tiof port output fall time 10 35 ns 22 tinhl int pin high or low time 25 * ns 23 trbhl rb7:rb0 change int high or low time 25 * ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: measurements are taken in ec mode where osc2 output = 4 x t osc = t cy . osc1 osc2 ? i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 15 11 12 16 old value new value ? in ec and rc modes only.
1996 microchip technology inc. ds30412c-page 157 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100 * ns 31 twdt watchdog timer time-out period (prescale = 1) 5 * 12 25 * ms 32 tost oscillation start-up timer period 1024 t osc ?st osc = osc1 period 33 tpwrt power-up timer period 40 * 96 200 * ms 35 tmcl2adi mclr to system interface bus (ad15:ad0) invalid 100 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. this speci?ation ensured by design. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 address / data 35
pic17c4x ds30412c-page 158 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 17-5: timer0 clock timings table 17-5: timer0 clock requirements figure 17-6: timer1, timer2, and timer3 clock timings table 17-6: timer1, timer2, and timer3 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 42 tt0p t0cki period t cy + 40 n ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. parameter no. sym characteristic min typ ? max units conditions 45 tt123h tclk12 and tclk3 high time 0.5 t cy + 20 ns 46 tt123l tclk12 and tclk3 low time 0.5 t cy + 20 ns 47 tt123p tclk12 and tclk3 input period t cy + 40 n ns n = prescale value (1, 2, 4, 8) 48 tcke2tmri delay from selected external clock edge to timer increment 2t osc 6 tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. ra1/t0cki 40 41 42 tclk12 45 46 or tclk3 tmrx 48 48 47
1996 microchip technology inc. ds30412c-page 159 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 17-7: capture timings table 17-7: capture requirements figure 17-8: pwm timings table 17-8: pwm requirements parameter no. sym characteristic min typ? max units conditions 50 tccl capture1 and capture2 input low time 10 * ns 51 tcch capture1 and capture2 input high time 10 * ns 52 tccp capture1 and capture2 input period 2 t cy n ns n = prescale value (4 or 16) * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. parameter no. sym characteristic min typ? max units conditions 53 tccr pwm1 and pwm2 output rise time 10 * 35 * ns 54 tccf pwm1 and pwm2 output fall time 10 * 35 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. cap1 and cap2 (capture mode) 50 51 52 pwm1 and pwm2 (pwm mode) 53 54
pic17c4x ds30412c-page 160 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 17-9: usart module: synchronous transmission (master/slave) timing table 17-9: serial port synchronous transmission requirements figure 17-10: usart module: synchronous receive (master/slave) timing table 17-10: serial port synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid 65 ns 121 tckrf clock out rise time and fall time (master mode) ?035ns 122 tdtrf data out rise time and fall time 10 35 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 121 121 120 122 ra5/tx/ck ra4/rx/dt pin pin 125 126 ra5/tx/ck ra4/rx/dt pin pin
1996 microchip technology inc. ds30412c-page 161 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 17-11: memory interface write timing table 17-11: memory interface write requirements parameter no. sym characteristic min typ? max units conditions 150 tadv2all ad<15:0> (address) valid to ale (address setup time) 0.25tcy - 30 ns 151 tall2adi ale to address out invalid (address hold time) 0ns 152 tadv2wrl data out valid to wr (data setup time) 0.25tcy - 40 ns 153 twrh2adi wr to data out invalid (data hold time) 0.25t cy ns 154 twrl wr pulse width 0.25t cy ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation is guaranteed by design. osc1 ale oe wr ad<15:0> q1 q2 q3 q4 q1 q2 150 151 152 153 154 addr out data out addr out
pic17c4x ds30412c-page 162 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 17-12: memory interface read timing table 17-12: memory interface read requirements parameter no. sym characteristic min typ? max units conditions 150 tadv2all ad<15:0> (address) valid to ale (address setup time) 0.25tcy - 30 ns 151 tall2adi ale to address out invalid (address hold time) 5* ns 160 tadz2oel ad<15:0> high impedance to oe 0* ns 161 toeh2add oe to ad<15:0> driven 0.25tcy - 15 ns 162 tadv2oeh data in valid before oe (data setup time) 35 ns 163 toeh2adi oe to data in invalid (data hold time) 0 ns 164 talh ale pulse width 0.25t cy ns 165 toel oe pulse width 0.5tcy - 35 ns 166 talh2alh ale to ale (cycle time) t cy ns 167 tacc address access time 0.75 t cy -40 ns 168 toe output enable access time (oe low to data valid) 0.5 t cy - 60 ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation guaranteed by design. osc1 ale oe ad<15:0> wr q1 q2 q3 data in addr out 150 151 160 166 165 163 161 '1' '1' q4 q1 q2 addr out 164 168 167 162
1996 microchip technology inc. ds30412c-page 163 pic17c4x applicable devices 42 r42 42a 43 r43 44 18.0 pic17c42 dc and ac characteristics the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside speci?d operating range (e.g. outside speci?d v dd range). this is for infor- mation only and devices are ensured to operate properly only within the speci?d range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "typical" represents the mean of the distribution while "max" or "min" represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation. table 18-1: pin capacitance per package type figure 18-1: typical rc oscillator frequency vs. temperature pin name typical capacitance (pf) 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp all pins, except mclr , v dd , and v ss 10 10 10 10 mclr pin 20 20 20 20 f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5v v dd = 3.5v rext 10 k w cext = 100 pf this document was created with framemake r404
pic17c4x ds30412c-page 164 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 18-2: typical rc oscillator frequency vs. v dd figure 18-3: typical rc oscillator frequency vs. v dd 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 22 pf, t = 25 c r = 100k 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 100 pf, t = 25 c r = 100k r = 3.3k r = 5.1k
1996 microchip technology inc. ds30412c-page 165 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 18-4: typical rc oscillator frequency vs. v dd table 18-2: rc oscillator frequencies cext rext average fosc @ 5v, 25 c 22 pf 10k 3.33 mhz 12% 100k 353 khz 13% 100 pf 3.3k 3.54 mhz 10% 5.1k 2.43 mhz 14% 10k 1.30 mhz 17% 100k 129 khz 10% 300 pf 3.3k 1.54 mhz 14% 5.1k 980 khz 12% 10k 564 khz 16% 160k 35 khz 18% 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 300 pf, t = 25 c r = 160k r = 3.3k r = 5.1k 0.2 0.0
pic17c4x ds30412c-page 166 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 18-5: transconductance (gm) of lf oscillator vs. v dd figure 18-6: transconductance (gm) of xt oscillator vs. v dd 500 450 400 350 300 250 200 150 100 2.5 3.0 3.5 4.0 4.5 5.0 gm( m a/v) v dd (volts) min @ 85 c 50 0 5.5 6.0 max @ -40 c typ @ 25 c 20 18 16 14 12 10 8 6 4 2.5 3.0 3.5 4.0 4.5 5.0 gm(ma/v) v dd (volts) min @ 85 c 2 0 5.5 6.0 max @ -40 c typ @ 25 c
1996 microchip technology inc. ds30412c-page 167 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 18-7: typical i dd vs. frequency (external clock 25 c) figure 18-8: maximum i dd vs. frequency (external clock 125 c to -40 c) 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 7.0v 10 6.5v 6.0v 5.5v 4.5v 5.0v 4.0v 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 6.5v 6.0v 5.5v 4.0v 4.5v 5.0v 7.0v
pic17c4x ds30412c-page 168 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 18-9: typical i pd vs. v dd watchdog disabled 25 c figure 18-10: maximum i pd vs. v dd watchdog disabled 12 10 8 6 4 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 2 0 6.5 7.0 600 500 400 300 200 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 100 0 6.5 7.0 1300 1200 1100 1000 900 800 700 1900 1800 1700 1600 1500 1400 temp. = 85 c temp. = 70 c temp. = 0 c temp. = -40 c
1996 microchip technology inc. ds30412c-page 169 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 18-11: typical i pd vs. v dd watchdog enabled 25 c figure 18-12: maximum i pd vs. v dd watchdog enabled 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 5 0 6.5 7.0 60 50 40 30 20 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 10 0 6.5 7.0 -40 c 0 c 70 c 85 c
pic17c4x ds30412c-page 170 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 18-13: wdt timer time-out period vs. v dd figure 18-14: i oh vs. v oh , v dd = 3v 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 v dd (volts) 5 0 6.5 7.0 wdt period (ms) max. 70 c typ. 25 c min. 0 c min. -40 c max. 85 c 0 -2 -4 -6 -8 -10 -12 -14 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) min @ 85 c -16 -18 3.0 max @ -40 c typ @ 25 c
1996 microchip technology inc. ds30412c-page 171 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 18-15: i oh vs. v oh , v dd = 5v figure 18-16: i ol vs. v ol , v dd = 3v 0 -5 -10 -15 -20 -25 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) -30 -35 3.0 max @ -40 c typ @ 25 c 3.5 4.0 4.5 5.0 min @ 85 c 30 25 20 15 10 0.0 0.5 1.0 1.5 2.0 v dd (volts) 5 0 2.5 3.0 i ol (ma) min. +85 c typ. 25 c max. -40 c
pic17c4x ds30412c-page 172 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 18-17: i ol vs. v ol , v dd = 5v figure 18-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd 90 80 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) min @ +85 c 10 0 3.0 max @ -40 c typ @ 25 c typ @ 25 c 2.5 v th (volts) v dd (volts) 0.6 max (-40 c to +85 c) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 min (-40 c to +85 c)
1996 microchip technology inc. ds30412c-page 173 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 18-19: v th , v il of i/o pins (schmitt trigger) vs . v dd figure 18-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd 2.0 v ih , v il (volts) v dd (volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 4.0 4.5 5.0 v ih , max (-40 c to +85 c) v ih , typ (25 c) v ih , min (-40 c to +85 c) v il , max (-40 c to +85 c) v il , typ (25 c) v il , min (-40 c to +85 c) v th ,(volts) v dd (volts) 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.2 1.4 1.6 1.8 2.0 2.2 2.4 6.0 2.6 2.8 3.0 min (-40 c to +85 c) 3.2 3.4 max (-40 c to +85 c) typ (25 c)
pic17c4x ds30412c-page 174 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 175 pic17c4x applicable devices 42 r42 42a 43 r43 44 19.0 pic17cr42/42a/43/r43/44 electrical characteristics absolute maximum ratings ? ambient temperature under bias..................................................................................................................-55 to +125?c storage temperature ............................................................................................................................... -65?c to +150?c voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) ..........................................................................................-0.6v to +14v voltage on ra2 and ra3 with respect to v ss ..............................................................................................-0.6v to +14v voltage on all other pins with respect to v ss ..................................................................................... -0.6v to v dd + 0.6v total power dissipation (note 1).................................................................................................................................1.0w maximum current out of v ss pin(s) - total ..............................................................................................................250 ma maximum current into v dd pin(s) - total .................................................................................................................200 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin (except ra2 and ra3)......................................................................35 ma maximum output current sunk by ra2 or ra3 pins .................................................................................................60 ma maximum output current sourced by any i/o pin .....................................................................................................20 ma maximum current sunk by porta and portb (combined)..................................................................................150 ma maximum current sourced by porta and portb (combined).............................................................................100 ma maximum current sunk by portc, portd and porte (combined)...................................................................150 ma maximum current sourced by portc, portd and porte (combined)..............................................................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a "low" level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic17c4x ds30412c-page 176 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic17lcr42-08 pic17lc42a-08 pic17lc43-08 pic17lcr43-08 pic17lc44-08 pic17cr42-16 pic17c42a-16 pic17c43-16 pic17cr43-16 pic17c44-16 pic17cr42-25 pic17c42a-25 pic17c43-25 pic17cr43-25 pic17c44-25 pic17cr42-33 pic17c42a-33 pic17c43-33 pic17cr43-33 pic17c44-33 jw devices (ceramic windowed devices) rc v dd : 2.5v to 6.0v i dd : 6 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 4 mhz max. v dd : 4.5v to 6.0v i dd : 6 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 4 mhz max. v dd : 4.5v to 6.0v i dd : 6 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 4 mhz max. v dd : 4.5v to 6.0v i dd : 6 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 4 mhz max. v dd : 4.5v to 6.0v i dd : 6 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 4 mhz max. xt v dd : 2.5v to 6.0v i dd : 12 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 8 mhz max. v dd : 4.5v to 6.0v i dd : 24 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 16 mhz max. v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 25 mhz max. v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 33 mhz max. v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 33 mhz max. ec v dd : 2.5v to 6.0v i dd : 12 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 8 mhz max. v dd : 4.5v to 6.0v i dd : 24 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 16 mhz max v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 25 mhz max. v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 33 mhz max. v dd : 4.5v to 6.0v i dd : 38 ma max. i pd : 5 m a max. at 5.5v wdt disabled freq: 33 mhz max. lf v dd : 2.5v to 6.0v i dd : 150 m a max. at 32 khz i pd : 5 m a max. at 5.5v wdt disabled freq: 2 mhz max. v dd : 4.5v to 6.0v i dd : 95 m a typ. at 32 khz i pd : < 1 m a typ. at 5.5v wdt disabled freq: 2 mhz max. v dd : 4.5v to 6.0v i dd : 95 m a typ. at 32 khz i pd : < 1 m a typ. at 5.5v wdt disabled freq: 2 mhz max. v dd : 4.5v to 6.0v i dd : 95 m a typ. at 32 khz i pd : < 1 m a typ. at 5.5v wdt disabled freq: 2 mhz max. v dd : 2.5v to 6.0v i dd : 150 m a max. at 32 khz i pd : 5 m a max. at 5.5v wdt disabled freq: 2 mhz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max specications. it is recommended that the user select the device type that ensures the specications required.
1996 microchip technology inc. ds30412c-page 177 pic17c4x applicable devices 42 r42 42a 43 r43 44 19.1 dc characteristics: pic17cr42/42a/43/r43/44-16 (commercial, industrial) pic17cr42/42a/43/r43/44-25 (commercial, industrial) pic17cr42/42a/43/r43/44-33 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial parameter no. sym characteristic min typ? max units conditions d001 v dd supply voltage 4.5 6.0 v d002 v dr ram data retention voltage (note 1) 1.5 * v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.060 * mv/ms see section on power-on reset for details d010 d011 d012 d013 d015 d014 i dd supply current (note 2) 3 6 11 19 25 95 6 12 * 24 * 38 50 150 ma ma ma ma ma m a f osc = 4 mhz (note 4) f osc = 8 mhz f osc = 16 mhz f osc = 25 mhz f osc = 33 mhz f osc = 32 khz, wdt enabled (ec osc con?uration) d020 d021 i pd power-down current (note 3) 10 < 1 40 5 m a m a v dd = 5.5v, wdt enabled v dd = 5.5v, wdt disabled * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd or v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. current consumed from the oscillator and i/os driving external capacitive or resistive loads needs to be con- sidered. for the rc oscillator, the current through the external pull-up resistor (r) can be estimated as: v dd / (2 r). for capacitive loads, the current can be estimated (for an individual i/o pin) as (c l v dd ) f c l = total capacitive load on the i/o pin; f = average frequency the i/o pin switches. the capacitive currents are most signi?ant when the device is con?ured for external execution (includes extended microcontroller mode). 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm.
pic17c4x ds30412c-page 178 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 19.2 dc characteristics: pic17lc42a/43/lc44 (commercial, industrial) pic17lcr42/43 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial parameter no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 6.0 v d002 v dr ram data retention voltage (note 1) 1.5 * v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.060 * mv/ms see section on power-on reset for details d010 d011 d014 i dd supply current (note 2) 3 6 95 6 12 * 150 ma ma m a f osc = 4 mhz (note 4) f osc = 8 mhz f osc = 32 khz, wdt disabled (ec osc con?uration) d020 d021 i pd power-down current (note 3) 10 < 1 40 5 m a m a v dd = 5.5v, wdt enabled v dd = 5.5v, wdt disabled * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd or v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. current consumed from the oscillator and i/os driving external capacitive or resistive loads needs to be con- sidered. for the rc oscillator, the current through the external pull-up resistor (r) can be estimated as: v dd / (2 r). for capacitive loads, the current can be estimated (for an individual i/o pin) as (c l v dd ) f c l = total capacitive load on the i/o pin; f = average frequency the i/o pin switches. the capacitive currents are most signi?ant when the device is con?ured for external execution (includes extended microcontroller mode). 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm.
1996 microchip technology inc. ds30412c-page 179 pic17c4x applicable devices 42 r42 42a 43 r43 44 19.3 dc characteristics: pic17cr42/42a/43/r43/44-16 (commercial, industrial) pic17cr42/42a/43/r43/44-25 (commercial, industrial) pic17cr42/42a/43/r43/44-33 (commercial, industrial) pic17lcr42/42a/43/r43/44-08 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 19.1 parameter no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss v ss 0.8 0.2v dd v v 4.5v v dd 5.5v 2.5v v dd 4.5v d031 with schmitt trigger buffer v ss 0.2v dd v d032 mclr , osc1 (in ec and rc mode) vss 0.2v dd v note1 d033 osc1 (in xt, and lf mode) 0.5v dd ? input high voltage v ih i/o ports d040 with ttl buffer 2.0 1 + 0.2v dd v dd v dd v v 4.5v v dd 5.5v 2.5v v dd 4.5v d041 with schmitt trigger buffer 0.8v dd ? dd v d042 mclr 0.8v dd ? dd v note1 d043 osc1 (xt, and lf mode) 0.5v dd ? d050 v hys hysteresis of schmitt trigger inputs 0.15v dd * v input leakage current (notes 2, 3) d060 i il i/o ports (except ra2, ra3) 1 m a vss ? v pin ? v dd , i/o pin at hi-impedance portb weak pull-ups disabled d061 mclr 2 m av pin = vss or v pin = v dd d062 ra2, ra3 2 m a vss ? v ra 2, v ra 3 12v d063 osc1, test (ec, rc modes) 1 m a vss ? v pin ? v dd d063b osc1, test (xt, lf modes) v pin m ar f 1 m w , see figure 14.2 d064 mclr 10 m av mclr = v pp = 12v (when not programming) d070 i purb portb weak pull-up current 60 200 400 m a v pin = v ss , rbpu = 0 4.5v ? v dd ? 6.0v * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator conguration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specied levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is dened as coming out of the pin. 4: these specications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specications can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two specications may be used.
pic17c4x ds30412c-page 180 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 output low voltage d080 d081 v ol i/o ports (except ra2 and ra3) with ttl buffer 0.1v dd 0.1v dd * 0.4 v v v i ol = v dd /1.250 ma 4.5v v dd 6.0v v dd = 2.5v i ol = 6 ma, v dd = 4.5v note 6 d082 ra2 and ra3 3.0 v i ol = 60.0 ma, v dd = 6.0v d083 d084 osc2/clkout (rc and ec osc modes) 0.4 0.1v dd * v v i ol = 1 ma, v dd = 4.5v i ol = v dd /5 ma (pic17lc43/lc44 only) output high voltage (note 3) d090 d091 v oh i/o ports (except ra2 and ra3) with ttl buffer 0.9v dd 0.9v dd * 2.4 v v v i oh = -v dd /2.500 ma 4.5v v dd 6.0v v dd = 2.5v i oh = -6.0 ma, v dd =4.5v note 6 d092 ra2 and ra3 12 v pulled-up to externally applied voltage d093 d094 osc2/clkout (rc and ec osc modes) 2.4 0.9v dd * v v i oh = -5 ma, v dd = 4.5v i oh = -v dd /5 ma (pic17lc43/lc44 only) capacitive loading specs on output pins d100 c osc2 osc2/clkout pin 25 pf in ec or rc osc modes when osc2 pin is outputting clkout. external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) 50 pf d102 c ad system interface bus (portc, portd and porte) 50 pf in microprocessor or extended microcontroller mode dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 19.1 parameter no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator conguration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specied levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is dened as coming out of the pin. 4: these specications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specications can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two specications may be used.
1996 microchip technology inc. ds30412c-page 181 pic17c4x applicable devices 42 r42 42a 43 r43 44 dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +40?c operating voltage v dd range as described in section 19.1 parameter no. sym characteristic min typ? max units conditions internal program memory programming specs (note 4) d110 d111 d112 d113 d114 v pp v ddp i pp i ddp t prog voltage on mclr /v pp pin supply voltage during programming current into mclr /v pp pin supply current during programming programming pulse width 12.75 4.75 10 5.0 25 100 13.25 5.25 50 30 1000 v v ma ma m s note 5 terminated via internal/ external interrupt or a reset * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as coming out of the pin. 4: these speci?ations are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming speci?ations can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two speci?ations may be used. note: when using the table write for internal programming, the device temperature must be less than 40?c.
pic17c4x ds30412c-page 182 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 19.4 timing p ara meter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase symbols (pp) and their meanings: pp ad address/data ost oscillator start-up timer al ale pwrt power-up timer cc capture1 and capture2 rb portb ck clkout or clock rd rd dt data in rw rd or wr in int pin t0 t0cki io i/o port t123 tclk12 and tclk3 mc mclr wdt watchdog timer oe oe wr wr os osc1 uppercase symbols and their meanings: s d driven l low e edge p period f fall r rise h high v valid i invalid (hi-impedance) z hi-impedance
1996 microchip technology inc. ds30412c-page 183 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 19-1: parameter measurement information all timings are measure between high and low measurement points as indicated in the ?ures below. 0.9 v dd 0.1 v dd rise time fall time v oh = 0.7v dd v dd /2 v ol = 0.3v dd data out valid data out invalid output hi-impedance output driven 0.25v 0.25v 0.25v 0.25v output level conditions portc, d and e pins all other input pins v ih = 2.4v v il = 0.4v data in valid data in invalid v ih = 0.9v dd v il = 0.1v dd data in valid data in invalid input level conditions load conditions load condition 1 pin c l v ss 50 pf c l
pic17c4x ds30412c-page 184 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 19.5 timing dia grams and speci cations figure 19-2: external clock timing table 19-2: external clock timing requirements param no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc dc dc dc 8 16 25 33 mhz mhz mhz mhz ec osc mode - 08 devices (8 mhz devices) - 16 devices (16 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) oscillator frequency (note 1) dc 1 1 1 1 dc 4 8 16 25 33 2 mhz mhz mhz mhz mhz mhz rc osc mode xt osc mode - 08 devices (8 mhz devices) - 16 devices (16 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) lf osc mode 1 tosc external clkin period (note 1) 125 62.5 40 30.3 ns ns ns ns ec osc mode - 08 devices (8 mhz devices) - 16 devices (16 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) oscillator period (note 1) 250 125 62.5 40 30.3 500 1,000 1,000 1,000 1,000 ns ns ns ns ns ns rc osc mode xt osc mode - 08 devices (8 mhz devices) - 16 devices (16 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) lf osc mode 2t cy instruction cycle time (note 1) 121.2 4/fosc dc ns 3 tosl, tosh clock in (osc1) high or low time 10 ns ec oscillator 4 tosr, tosf clock in (osc1) rise or fall time 5 ns ec oscillator ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?in. values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ?ax. cycle time limit is ?c (no clock) for all devices. osc1 osc2 ? q4 q1 q2 q3 q4 q1 1 3 3 4 4 2 ? in ec and rc modes only.
1996 microchip technology inc. ds30412c-page 185 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 19-3: clkout and i/o timing table 19-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 to clkout 15 30 ns note 1 11 tosh2ckh osc1 to clkout 15 30 ns note 1 12 tckr clkout rise time 5 15 ns note 1 13 tckf clkout fall time 5 15 ns note 1 14 tckh2iov clkout to port out valid pic17cr42/42a/43/ r43/44 0.5t cy + 20 ns note 1 pic17lcr42/42a/43/ r43/44 0.5t cy + 50 ns note 1 15 tiov2ckh port in valid before clkout pic17cr42/42a/43/ r43/44 0.25t cy + 25 ns note 1 pic17lcr42/42a/43/ r43/44 0.25t cy + 50 ns note 1 16 tckh2ioi port in hold after clkout 0 ns note 1 17 tosh2iov osc1 (q1 cycle) to port out valid 100 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) 0 ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 30 ns 20 tior port output rise time 10 35 ns 21 tiof port output fall time 10 35 ns 22 tinhl int pin high or low time 25 * ns 23 trbhl rb7:rb0 change int high or low time 25 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: measurements are taken in ec mode where clkout output is 4 x t osc . osc1 osc2 ? i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value ? in ec and rc modes only.
pic17c4x ds30412c-page 186 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 19-4: reset, watchdog timer, oscillator start-up timer, and power-up timer timing table 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100 * ns v dd = 5v 31 twdt watchdog timer time-out period (prescale = 1) 5 * 12 25 * ms v dd = 5v 32 tost oscillation start-up timer period 1024t osc ms t osc = osc1 period 33 tpwrt power-up timer period 40 * 96 200 * ms v dd = 5v 35 tmcl2adi mclr to system inter- face bus (ad15:ad0>) invalid pic17cr42/42a/ 43/r43/44 100 * ns pic17lcr42/ 42a/43/r43/44 120 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. this speci?ation ensured by design. v dd mclr internal por pwrt timeout osc timeout internal reset watchdog timer reset 33 32 30 31 address / data 35
1996 microchip technology inc. ds30412c-page 187 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 19-5: timer0 clock timings table 19-5: timer0 clock requirements figure 19-6: timer1, timer2, and timer3 clock timings table 19-6: timer1, timer2, and timer3 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 ns or t cy + 40 n ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. parameter no. sym characteristic min typ ? max units conditions 45 tt123h tclk12 and tclk3 high time 0.5t cy + 20 ns 46 tt123l tclk12 and tclk3 low time 0.5t cy + 20 ns 47 tt123p tclk12 and tclk3 input period t cy + 40 n ns n = prescale value (1, 2, 4, 8) 48 tcke2tmri delay from selected external clock edge to timer increment 2t osc 6tosc * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. ra1/t0cki 40 41 42 tclk12 45 46 or tclk3 tmrx 48 48 47
pic17c4x ds30412c-page 188 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 19-7: capture timings table 19-7: capture requirements figure 19-8: pwm timings table 19-8: pwm requirements parameter no. sym characteristic min typ? max units conditions 50 tccl capture1 and capture2 input low time 10 * ns 51 tcch capture1 and capture2 input high time 10 * ns 52 tccp capture1 and capture2 input period 2 t cy n ns n = prescale value (4 or 16) * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. parameter no. sym characteristic min typ? max units conditions 53 tccr pwm1 and pwm2 output rise time 10 * 35 * ns 54 tccf pwm1 and pwm2 output fall time 10 * 35 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. cap1 and cap2 (capture mode) 50 51 52 pwm1 and pwm2 (pwm mode) 53 54
1996 microchip technology inc. ds30412c-page 189 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 19-9: usart module: synchronous transmission (master/slave) timing table 19-9: synchronous transmission requirements figure 19-10: usart module: synchronous receive (master/slave) timing table 19-10: synchronous receive requirements param no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve ) clock high to data out valid pic17cr42/42a/43/r43/44 50 ns pic17lcr42/42a/43/r43/44 75 ns 121 tckrf clock out rise time and fall time (master mode) pic17cr42/42a/43/r43/44 25 ns pic17lcr42/42a/43/r43/44 40 ns 122 tdtrf data out rise time and fall time pic17cr42/42a/43/r43/44 25 ns pic17lcr42/42a/43/r43/44 40 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 121 121 120 122 ra5/tx/ck ra4/rx/dt pin pin 125 126 ra5/tx/ck ra4/rx/dt pin pin
pic17c4x ds30412c-page 190 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 19-11: memory interface write timing (not supported in pic17lc4x devices) table 19-11: memory interface write requirements (not supported in pic17lc4x devices) parameter no. sym characteristic min typ? max units conditions 150 tadv2all ad<15:0> (address) valid to ale (address setup time) 0.25tcy - 10 ns 151 tall2adi ale to address out invalid (address hold time) 0ns 152 tadv2wrl data out valid to wr (data setup time) 0.25tcy - 40 ns 153 twrh2adi wr to data out invalid (data hold time) 0.25t cy ns 154 twrl wr pulse width 0.25t cy ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. osc1 ale oe wr ad<15:0> q1 q2 q3 q4 q1 q2 150 151 152 153 154 addr out data out addr out
1996 microchip technology inc. ds30412c-page 191 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 19-12: memory interface read timing (not supported in pic17lc4x devices) table 19-12: memory interface read requirements (not supported in pic17lc4x devices) parameter no. sym characteristic min typ? max units conditions 150 tadv2all ad15:ad0 (address) valid to ale (address setup time) 0.25tcy - 10 ns 151 tall2adi ale to address out invalid (address hold time) 5* ns 160 tadz2oel ad15:ad0 hi-impedance to oe 0* ns 161 toeh2add oe to ad15:ad0 driven 0.25tcy - 15 ns 162 tadv2oeh data in valid before oe (data setup time) 35 ns 163 toeh2adi oe to data in invalid (data hold time) 0 ns 164 talh ale pulse width 0.25t cy ns 165 toel oe pulse width 0.5tcy - 35 ns 166 talh2alh ale to ale (cycle time) t cy ns 167 tacc address access time 0.75t cy - 30 ns 168 toe output enable access time (oe low to data valid) 0.5t cy - 45 ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. osc1 ale oe ad<15:0> wr q1 q2 q3 data in addr out 150 151 160 166 165 162 163 161 '1' '1' q4 q1 q2 addr out 164 168 167
pic17c4x ds30412c-page 192 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 193 pic17c4x applicable devices 42 r42 42a 43 r43 44 20.0 pic17cr42/42a/43/r43/44 dc and ac characteristics the graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. in some graphs or tables the data presented is outside speci?d operating range (e.g. outside speci?d v dd range). this is for information only and devices are ensured to operate properly only within the speci?d range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "typical" represents the mean of the distribution while "max" or "min" represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation. table 20-1: pin capacitance per package type figure 20-1: typical rc oscillator frequency vs. temperature pin name typical capacitance (pf) 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp all pins, except mclr , v dd , and v ss 10 10 10 10 mclr pin 20 20 20 20 f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5v v dd = 3.5v rext 10 k w cext = 100 pf this document was created with framemake r404
pic17c4x ds30412c-page 194 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 20-2: typical rc oscillator frequency vs. v dd figure 20-3: typical rc oscillator frequency vs. v dd 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 22 pf, t = 25 c r = 100k 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 100 pf, t = 25 c r = 100k r = 3.3k r = 5.1k
1996 microchip technology inc. ds30412c-page 195 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 20-4: typical rc oscillator frequency vs. v dd table 20-2: rc oscillator frequencies cext rext average fosc @ 5v, 25 c 22 pf 10k 3.33 mhz 12% 100k 353 khz 13% 100 pf 3.3k 3.54 mhz 10% 5.1k 2.43 mhz 14% 10k 1.30 mhz 17% 100k 129 khz 10% 300 pf 3.3k 1.54 mhz 14% 5.1k 980 khz 12% 10k 564 khz 16% 160k 35 khz 18% 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 300 pf, t = 25 c r = 160k r = 3.3k r = 5.1k 0.2 0.0
pic17c4x ds30412c-page 196 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 20-5: transconductance (gm) of lf oscillator vs. v dd figure 20-6: transconductance (gm) of xt oscillator vs. v dd 500 450 400 350 300 250 200 150 100 2.5 3.0 3.5 4.0 4.5 5.0 gm( m a/v) v dd (volts) min @ 85 c 50 0 5.5 6.0 max @ -40 c typ @ 25 c 20 18 16 14 12 10 8 6 4 2.5 3.0 3.5 4.0 4.5 5.0 gm(ma/v) v dd (volts) min @ 85 c 2 0 5.5 6.0 max @ -40 c typ @ 25 c
1996 microchip technology inc. ds30412c-page 197 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 20-7: typical i dd vs. frequency (external clock 25 c) figure 20-8: maximum i dd vs. frequency (external clock 125 c to -40 c) 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 7.0v 10 6.5v 6.0v 5.5v 4.5v 5.0v 4.0v 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 6.5v 6.0v 5.5v 4.0v 4.5v 5.0v 7.0v
pic17c4x ds30412c-page 198 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 20-9: typical i pd vs. v dd watchdog disabled 25 c figure 20-10: maximum i pd vs. v dd watchdog disabled 12 10 8 6 4 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 2 0 6.5 7.0 600 500 400 300 200 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 100 0 6.5 7.0 1300 1200 1100 1000 900 800 700 1900 1800 1700 1600 1500 1400 temp. = 85 c temp. = 70 c temp. = 0 c temp. = -40 c
1996 microchip technology inc. ds30412c-page 199 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 20-11: typical i pd vs. v dd watchdog enabled 25 c figure 20-12: maximum i pd vs. v dd watchdog enabled 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 5 0 6.5 7.0 60 50 40 30 20 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 10 0 6.5 7.0 -40 c 0 c 70 c 85 c
pic17c4x ds30412c-page 200 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 20-13: wdt timer time-out period vs. v dd figure 20-14: i oh vs. v oh , v dd = 3v 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 v dd (volts) 5 0 6.5 7.0 wdt period (ms) max. 70 c typ. 25 c min. 0 c min. -40 c max. 85 c 0 -2 -4 -6 -8 -10 -12 -14 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) min @ 85 c -16 -18 3.0 max @ -40 c typ @ 25 c
1996 microchip technology inc. ds30412c-page 201 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 20-15: i oh vs. v oh , v dd = 5v figure 20-16: i ol vs. v ol , v dd = 3v 0 -5 -10 -15 -20 -25 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) -30 -35 3.0 max @ -40 c typ @ 25 c 3.5 4.0 4.5 5.0 min @ 85 c 30 25 20 15 10 0.0 0.5 1.0 1.5 2.0 v dd (volts) 5 0 2.5 3.0 i ol (ma) min. +85 c typ. 25 c max. -40 c
pic17c4x ds30412c-page 202 1996 microchip technology inc. applicable devices 42 r42 42a 43 r43 44 figure 20-17: i ol vs. v ol , v dd = 5v figure 20-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd 90 80 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v dd (volts) min @ +85 c 10 0 3.0 max @ -40 c typ @ 25 c 2.5 v th (volts) v dd (volts) 0.6 max (-40 c to +85 c) typ @ 25 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 min (-40 c to +85 c)
1996 microchip technology inc. ds30412c-page 203 pic17c4x applicable devices 42 r42 42a 43 r43 44 figure 20-19: v th , v il of i/o pins (schmitt trigger) vs . v dd figure 20-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd 2.0 v ih , v il (volts) v dd (volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 4.0 4.5 5.0 v ih , max (-40 c to +85 c) v ih , typ (25 c) v ih , min (-40 c to +85 c) v il , max (-40 c to +85 c) v il , typ (25 c) v il , min (-40 c to +85 c) v th ,(volts) v dd (volts) 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.2 1.4 1.6 1.8 2.0 2.2 2.4 6.0 2.6 2.8 3.0 min (-40 c to +85 c) 3.2 3.4 max (-40 c to +85 c) typ (25 c)
pic17c4x ds30412c-page 204 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 205 pic17c4x 21.0 packaging information 21.1 40-lead ceramic cerdip dual in-line , and cerdip dual in-line with windo w (600 mil) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.318 5.715 0.170 0.225 a1 0.381 1.778 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.435 52.705 2.025 2.075 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 12.954 15.240 0.510 0.600 e1 2.540 2.540 reference 0.100 0.100 reference ea 14.986 16.002 typical 0.590 0.630 typical eb 15.240 18.034 0.600 0.710 l 3.175 3.810 0.125 0.150 n 4040 4040 s 1.016 2.286 0.040 0.090 s1 0.381 1.778 0.015 0.070 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a a2 l e1 a c e a e b this document was created with framemake r404
pic17c4x ds30412c-page 206 1996 microchip technology inc. 21.2 40-lead plastic dual in-line (600 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 0.015 a2 3.175 4.064 0.125 0.160 b 0.355 0.559 0.014 0.022 b1 1.270 1.778 typical 0.050 0.070 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.181 52.197 2.015 2.055 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 13.462 13.970 0.530 0.550 e1 2.489 2.591 typical 0.098 0.102 typical ea 15.240 15.240 reference 0.600 0.600 reference eb 15.240 17.272 0.600 0.680 l 2.921 3.683 0.115 0.145 n 4040 4040 s 1.270 0.050 s1 0.508 0.020 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1996 microchip technology inc. ds30412c-page 207 pic17c4x 21.3 44-lead plastic leaded chip carrier (square) package group: plastic leaded chip carrier (plcc) symbol millimeters inches min max notes min max notes a 4.191 4.572 0.165 0.180 a1 2.413 2.921 0.095 0.115 d 17.399 17.653 0.685 0.695 d1 16.510 16.663 0.650 0.656 d2 15.494 16.002 0.610 0.630 d3 12.700 12.700 reference 0.500 0.500 reference e 17.399 17.653 0.685 0.695 e1 16.510 16.663 0.650 0.656 e2 15.494 16.002 0.610 0.630 e3 12.700 12.700 reference 0.500 0.500 reference n 4444 4444 cp 0.102 0.004 lt 0.203 0.381 0.008 0.015 s 0.177 .007 b d-e -a- 0.254 d 1 d 3 3 3 -c- -f- -d- 4 9 8 -b- -e- s 0.177 .007 a f-g s s e e 1 -h- -g- 6 2 3 .010 max 1.524 .060 10 2 11 0.508 .020 1.651 .065 r 1.14/0.64 .045/.025 r 1.14/0.64 .045/.025 1.651 .065 0.508 .020 -h- 11 0.254 .010 max 6 min 0.812/0.661 .032/.026 3 -c- 0.64 .025 min 5 0.533/0.331 .021/.013 0.177 .007 m a f-g s , d-e s 1.27 .050 2 sides a s 0.177 .007 b a s d 3 /e 3 d 2 0.101 .004 0.812/0.661 .032/.026 s 0.38 .015 f-g 4 s 0.38 .015 f-g e 2 d -h- a 1 seating plane 2 sides n pics
pic17c4x ds30412c-page 208 1996 microchip technology inc. 21.4 44-lead plastic surface mount (mqfp 10x10 mm bod y 1.6/0.15 mm lead form) package group: plastic mqfp symbol millimeters inches min max notes min max notes a 0 7 0 7 a 2.000 2.350 0.078 0.093 a1 0.050 0.250 0.002 0.010 a2 1.950 2.100 0.768 0.083 b 0.300 0.450 typical 0.011 0.018 typical c 0.150 0.180 0.006 0.007 d 12.950 13.450 0.510 0.530 d1 9.900 10.100 0.390 0.398 d3 8.000 8.000 reference 0.315 0.315 reference e 12.950 13.450 0.510 0.530 e1 9.900 10.100 0.390 0.398 e3 8.000 8.000 reference 0.315 0.315 reference e 0.800 0.800 0.031 0.032 l 0.730 1.030 0.028 0.041 n 4444 4444 cp 0.102 0.004 index area 9 b typ 4x base plane a 2 e b a a 1 seating plane 6 d d 1 d 3 4 5 7 e 3 e 1 e 10 0.20 m a-b 0.05 mm/mm d hs s d 0.20 m a-b cs s d 7 5 4 0.20 m a-b cs s d 0.20 m a-b hs s d 0.05 mm/mm a-b c l 1.60 ref. 0.13/0.30 r 0.13 r min. 0.20 min. parting line a
1996 microchip technology inc. ds30412c-page 209 pic17c4x 21.5 44-lead plastic surface mount (tqfp 10x10 mm bod y 1.0/0.10 mm lead form) note 1: dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.25m/m (0.010? per side. d1 and e1 dimensions including mold mismatch. 2: dimension ? does not include dambar protrusion, allowable dambar protrusion shall be 0.08m/m (0.003?max. 3: this outline conforms to jedec ms-026. package group: plastic tqfp symbol millimeters inches min max notes min max notes a 1.00 1.20 0.039 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 d 11.75 12.25 0.463 0.482 d1 9.90 10.10 0.390 0.398 e 11.75 12.25 0.463 0.482 e1 9.90 10.10 0.390 0.398 l 0.45 0.75 0.018 0.030 e 0.80 bsc 0.031 bsc b 0.30 0.45 0.012 0.018 b1 0.30 0.40 0.012 0.016 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 n 4444 4444 q 0 7 0 7 d e d1 e1 pin#1 2 e 1.0?(0.039? ref. option 1 (top side) pin#1 2 option 2 (top side) 3.0?(0.118? ref. detail a detail b l 1.00 ref. a2 a1 a b b1 c c1 base metal detail a lead finish detail b 11 /13 (4x) 0 min 11 /13 (4x) q r 1 0.08 min r 0.08/0.20 gage plane 0.250 l l1 s 0.20 min 1.00 ref detail b
pic17c4x ds30412c-page 210 1996 microchip technology inc. 21.6 p ac ka g e mar king inf ormation 44-lead tqfp xxxxxxxxxx aabbcde xxxxxxxxxx xxxxxxxxxx 44-lead plcc xxxxxxxxxx aabbcde xxxxxxxxxx xxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip/cerdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxx aabbcde 40 lead cerdip windowed xxxxxxxxxxx example -25/tq 9450cat pic17c44 l247 example pic17c42 9445ccn -16i/l l013 l006 9441cca example pic17c43-25i/p pic17c44 9444cct example l184 /jw legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 44-lead mqfp xxxxxxxxxx aabbcde xxxxxxxxxx xxxxxxxxxx example -25/pt 9450cat pic17c44 l247
1996 microchip technology inc. ds30412c-page 211 pic17c4x appendix a: modifications the following is the list of modi?ations over the pic16cxx microcontroller family: 1. instruction word length is increased to 16-bit. this allows larger page sizes both in program memory (8 kwords verses 2 kwords) and regis- ter ?e (256 bytes versus 128 bytes). 2. four modes of operation: microcontroller, pro- tected microcontroller, extended microcontroller, and microprocessor. 3. 22 new instructions. the movf , tris and option instructions have been removed. 4. 4 new instructions for transferring data between data memory and program memory. this can be used to ?elf program the eprom program memory. 5. single cycle data memory to data memory trans- fers possible ( movpf and movfp instructions). these instructions do not affect the working reg- ister (wreg). 6. w register (wreg) is now directly addressable. 7. a pc high latch register (pclath) is extended to 8-bits. the pclatch register is now both readable and writable. 8. data memory paging is rede?ed slightly. 9. ddr registers replaces function of tris regis- ters. 10. multiple interrupt vectors added. this can decrease the latency for servicing the interrupt. 11. stack size is increased to 16 deep. 12. bsr register for data memory paging. 13. wake up from sleep operates slightly differ- ently. 14. the oscillator start-up timer (ost) and power-up timer (pwrt) operate in parallel and not in series. 15. portb interrupt on change feature works on all eight port pins. 16. tmr0 is 16-bit plus 8-bit prescaler. 17. second indirect addressing register added (fsr1 and fsr2). con?uration bits can select the fsr registers to auto-increment, auto-dec- rement, remain unchanged after an indirect address. 18. hardware multiplier added (8 x 8 16-bit) (pic17c43 and pic17c44 only). 19. peripheral modules operate slightly differently. 20. oscillator modes slightly rede?ed. 21. control/status bits and registers have been placed in different registers and the control bit for globally enabling interrupts has inverse polarity. 22. addition of a test mode pin. 23. in-circuit serial programming is not imple- mented. appendix b: compatibility to convert code written for pic16cxx to pic17cxx, the user should take the following steps: 1. remove any tris and option instructions, and implement the equivalent code. 2. separate the interrupt service routine into its four vectors. 3. replace: movf reg1, w with: movfp reg1, wreg 4. replace: movf reg1, w movwf reg2 with: movpf reg1, reg2 ; addr(reg1)<20h or movfp reg1, reg2 ; addr(reg2)<20h 5. ensure that all bit names and register names are updated to new data memory map location. 6. verify data memory banking. 7. verify mode of operation for indirect addressing. 8. verify peripheral routines for compatibility. 9. weak pull-ups are enabled on reset. to convert code from the pic17c42 to all the other pic17c4x devices, the user should take the following steps. 1. if the hardware multiply is to be used, ensure that any variables at address 18h and 19h are moved to another address. 2. ensure that the upper nibble of the bsr was not written with a non-zero value. this may cause unexpected operation since the ram bank is no longer 0. 3. the disabling of global interrupts has been enhanced so there is no additional testing of the glintd bit after a bsf cpusta, glintd instruction. note: if reg1 and reg2 are both at addresses greater then 20h, two instructions are required. movfp reg1, wreg ; movpf wreg, reg2 ; this document was created with framemake r404
pic17c4x ds30412c-page 212 1996 microchip technology inc. appendix c: whats new the structure of the document has been made consis- tent with other data sheets. this ensures that important topics are covered across all pic16/17 families. here is an overview of new features. added the following devices: pic17cr42 pic17c42a pic17cr43 a 33 mhz option is now available. appendix d: whats changed to make software more portable across the different pic16/17 families, the name of several registers and control bits have been changed. this allows control bits that have the same function, to have the same name (regardless of processor family). care must still be taken, since they may not be at the same special func- tion register address. the following shows the register and bit names that have been changed: instruction decfsnz corrected to dcfsnz instruction incfsnz corrected to infsnz enhanced discussion on pwm to include equation for determining bits of pwm resolution. section 13.2.2 and 13.3.2 have had the description of updating the ferr and rx9 bits enhanced. the location of con?uration bit pm2 was changed (figure 6-1 and figure 14-1). enhanced description of the operation of the intsta register. added note to discussion of interrupt operation. tightened electrical spec d110. corrected steps for setting up usart asynchronous reception. old name new name tx8/9 tx9 rc8/9 rx9 rcd8 rx9d txd8 tx9d
pic17c4x 1996 microchip technology inc. ds30412c-page 213 appendix e: pic16/17 microcontrollers e.1 pic14000 de vices pic14000 20 4k 192 tmr0 adtmr i 2 c/ smbus 14 11 22 2.7-6.0 yes internal oscillator, bandgap reference, temperature sensor, calibration factors, low voltage detector, sleep, hibernate, comparators with programmable references (2) 28-pin dip, soic, ssop (.300 mil) maximum frequency of operation (mhz) data memory (bytes) timer module(s) serial port(s) (spi/i 2 c, usart) slope a/d converter interrupt sources i/o pins voltage range (volts) eprom program memory (x14 words) clock memory peripherals features in-circuit serial programming additional on-chip features packages (high-res) channels this document was created with framemake r404
pic17c4x ds30412c-page 214 1996 microchip technology inc. e.2 pic16c5x f amil y of de vices pic16c52 4 384 25 tmr0 12 2.5-6.25 33 18-pin dip, soic pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. packages number of instructions voltage range (volts) i/o pins timer module(s) ram data memory (bytes) (x12 words) program memory rom eprom maximum frequency of operation (mhz) features peripherals memory clock
pic17c4x 1996 microchip technology inc. ds30412c-page 215 e.3 pic16cxxx f amil y of de vices pic16c554 20 512 80 tmr0 ? 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c556 20 1k 80 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c558 20 2k 128 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c620 20 512 80 tmr0 2 ye s 4 13 2.5-6.0 ye s 18-pin dip, soic; 20-pin ssop pic16c621 20 1k 80 tmr0 2 ye s 4 13 2.5-6.0 ye s 18-pin dip, soic; 20-pin ssop pic16c622 20 2k 128 tmr0 2 ye s 4 13 2.5-6.0 ye s 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c6xxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features (x14 words)
pic17c4x ds30412c-page 216 1996 microchip technology inc. e.4 pic16c6x f amil y of de vices pic16c62 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes 28-pin sdip, soic, ssop pic16c62a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16cr62 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c63 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16cr63 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c64 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c64a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr64 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16c65 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c65a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr65 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c6x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features rom in-circuit serial programming (x14 words)
pic17c4x 1996 microchip technology inc. ds30412c-page 217 e.5 pic16c7x f amil y of de vices pic16c710 20 512 36 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 3.0-6.0 yes 18-pin dip, soic pic16c711 20 1k 68 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes 28-pin sdip, soic pic16c73a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c7x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom program memory (x14 w ords) data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages clock memory peripherals features in-circuit serial programming
pic17c4x ds30412c-page 218 1996 microchip technology inc. e.6 pic16c8x f amil y of de vices pic16c84 10 1k 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eeprom data eeprom (bytes) data memory (bytes) timer module(s) interrupt sources i/o pins voltage range (volts) packages program memory clock memory peripherals features rom flash
pic17c4x 1996 microchip technology inc. ds30412c-page 219 e.7 pic16c9xx f amil y of de vices pic16c923 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 4 com 32 seg 8 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die pic16c924 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 5 4 com 32 seg 9 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip representative for availability of this package. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming input pins lcd module
pic17c4x ds30412c-page 220 1996 microchip technology inc. e.8 pic17cxx f amil y of de vices pic17c42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 4.5-5.5 55 40-pin dip; 44-pin plcc, mqfp pic17c42a 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17cr42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17c43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17cr43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17c44 25 8k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. maximum frequency of operation (mhz) eprom ram data memory (bytes) timer module(s) captures serial port(s) (usart) external interrupts interrupt sources i/o pins voltage range (volts) number of instructions packages clock memory peripherals features pwms hardware multiply program memory (words) rom
1996 microchip technology inc. ds30412c-page 221 pic17c4x pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table e-1: pin compatible devices pin compatible devices package pic12c508, pic12c509 8-pin pic16c54, pic16c54a, pic16cr54a, pic16c56, pic16c58a, pic16cr58a, pic16c61, pic16c554, pic16c556, pic16c558 pic16c620, pic16c621, pic16c622, pic16c710, pic16c71, pic16c711, pic16f83, pic16cr83, pic16c84, pic16f84a, pic16cr84 18-pin 20-pin pic16c55, pic16c57, pic16cr57b 28-pin pic16c62, pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73, pic16c73a 28-pin pic16c64, pic16cr64, pic16c64a, pic16c65, pic16c65a, pic16c74, pic16c74a 40-pin pic17c42, pic17cr42, pic17c42a, pic17c43, pic17cr43, pic17c44 40-pin pic16c923, pic16c924 64/68-pin
pic17c4x ds30412c-page 222 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 223 pic17c4x appendix f: errata for pic17c42 silicon the pic17c42 devices that you have received have the following anomalies. at present there is no intention for future revisions to the present pic17c42 silicon. if these cause issues for the application, it is recom- mended that you select the pic17c42a device. 1. when the oscillator start-up timer (ost) is enabled (in lf or xt oscillator modes), any inter- rupt that wakes the processor may cause a wdt reset. this occurs when the wdt is greater than or equal to 50% time-out period when the sleep instruction is executed. this will not occur in either the ec or rc oscillator modes. w or k-arounds a) always ensure that the clrwdt instruction is executed before the wdt increments past 50% of the wdt period. this will keep the ?alse wdt reset from occurring. b) when using the wdt as a normal timer (wdt disabled), ensure that the wdt is less than or equal to 50% time-out period when the sleep instruction is executed. this can be done by monitoring the t o bit for changing state from set to clear. example 1 shows putting the pic17c42 to sleep. example f-1: pic17c42 to sleep btfss cpusta, to ; to = 0? clrwdt ; yes, wdt = 0 loop btfsc cpusta, to ; wdt rollover? goto loop ; no, wait sleep ; yes, goto sleep 2. when the clock source of timer1 or timer2 is selected to external clock, the over?w interrupt ?g will be set twice, once when the timer equals the period, and again when the timer value is reset to 0h. if the latency to clear tmrxif is greater than the time to the next clock pulse, no problems will be noticed. if the latency is less than the time to the next timer clock pulse, the interrupt will be serviced twice. w or k-arounds a) ensure that the timer has rolled over to 0h before clearing the ?g bit. b) clear the timer in software. clearing the timer in software causes the period to be one count less than expected. note: new designs should use the pic17c42a. design considerations the device must not be operated outside of the speci- ?d voltage range. an external reset circuit must be used to ensure the device is in reset when a brown-out occurs or the v dd rise time is too long. failure to ensure that the device is in reset when device voltage is out of speci?ation may cause the device to lock-up and ignore the mclr pin. this document was created with framemake r404
pic17c4x ds30412c-page 224 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30412c-page 225 pic17c4x index a addlw ............................................................................ 112 addwf ............................................................................ 112 addwfc ......................................................................... 113 alu ...................................................................................... 9 alu status register (alusta) ..................................... 36 alusta ............................................................... 34, 36, 108 alusta register ............................................................... 36 andlw ............................................................................ 113 andwf ............................................................................ 114 application notes an552 ........................................................................ 55 assembler ........................................................................ 144 asynchronous master transmission .................................. 90 asynchronous transmitter ................................................. 89 b bank select register (bsr) ............................................... 42 banking .............................................................................. 42 baud rate formula ............................................................ 86 baud rate generator (brg) .............................................. 86 baud rates asynchronous mode .................................................. 88 synchronous mode .................................................... 87 bcf .................................................................................. 114 bit manipulation ............................................................... 108 block diagrams on-chip reset circuit ................................................. 15 pic17c42 .................................................................. 10 portd ...................................................................... 60 porte ....................................................................... 62 pwm .......................................................................... 75 ra0 and ra1 ............................................................. 53 ra2 and ra3 ............................................................. 54 ra4 and ra5 ............................................................. 54 rb3:rb2 port pins .................................................... 56 rb7:rb4 and rb1:rb0 port pins ............................. 55 rc7:rc0 port pins .................................................... 58 timer3 with one capture and one period register .. 78 tmr1 and tmr2 in 16-bit timer/counter mode ........ 74 tmr1 and tmr2 in two 8-bit timer/counter mode .. 73 tmr3 with two capture registers ............................ 79 wdt ......................................................................... 104 borrow ............................................................................ 9 brg ................................................................................... 86 brown-out protection ......................................................... 18 bsf .................................................................................. 115 bsr .............................................................................. 34, 42 bsr operation ................................................................... 42 btfsc ............................................................................. 115 btfss ............................................................................. 116 btg .................................................................................. 116 c c .................................................................................... 9, 36 c compiler (mp-c) .......................................................... 145 ca1/pr3 ............................................................................ 72 ca1ed0 ............................................................................. 71 ca1ed1 ............................................................................. 71 ca1ie .................................................................................23 ca1if .................................................................................24 ca1ovf .............................................................................72 ca2ed0 ..............................................................................71 ca2ed1 ..............................................................................71 ca2h ............................................................................20, 35 ca2ie ...........................................................................23, 78 ca2if ...........................................................................24, 78 ca2l .............................................................................20, 35 ca2ovf .............................................................................72 calculating baud rate error ...............................................86 call ...........................................................................39, 117 capacitor selection ceramic resonators .................................................101 crystal oscillator ......................................................101 capture .........................................................................71, 78 capture sequence to read example .................................78 capture1 mode ...........................................................................71 overflow .....................................................................72 capture2 mode ...........................................................................71 overflow .....................................................................72 carry (c) ...............................................................................9 ceramic resonators .........................................................100 circular buffer .....................................................................39 clearing the prescaler ......................................................103 clock/instruction cycle (figure) .........................................14 clocking scheme/instruction cycle (section) .....................14 clrf ................................................................................117 clrwdt ..........................................................................118 code protection ..........................................................99, 106 comf ...............................................................................118 configuration bits ............................................................................100 locations ..................................................................100 oscillator ...................................................................100 word ...........................................................................99 cpfseq ...........................................................................119 cpfsgt ...........................................................................119 cpfslt ............................................................................120 cpu status register (cpusta) ....................................37 cpusta ...............................................................34, 37, 105 cren .................................................................................84 crystal operation, overtone crystals ...............................101 crystal or ceramic resonator operation .........................100 crystal oscillator ..............................................................100 csrc .................................................................................83 d data memory gpr ......................................................................29, 32 indirect addressing .....................................................39 organization ...............................................................32 sfr ......................................................................29, 32 transfer to program memory .....................................43 daw .................................................................................120 dc ..................................................................................9, 36 ddrb .....................................................................19, 34, 55 ddrc .....................................................................19, 34, 58 ddrd .....................................................................19, 34, 60 ddre .....................................................................19, 34, 62 decf ................................................................................121 decfsnz .........................................................................122 decfsz ...........................................................................121 this document was created with framemake r404
pic17c4x ds30412c-page 226 1996 microchip technology inc. delay from external clock edge ....................................... 68 development support ...................................................... 143 development tools .......................................................... 143 device drawings 44-lead plastic surface mount (mqfp 10x10 mm body 1.6/0.15 mm lead form) .............. 209 digit borrow .................................................................. 9 digit carry (dc) .................................................................... 9 duty cycle .......................................................................... 75 e electrical characteristics pic17c42 absolute maximum ratings ............................. 147 capture timing ................................................ 159 clkout and i/o timing .................................. 156 dc characteristics ........................................... 149 external clock timing ...................................... 155 memory interface read timing ........................ 162 memory interface write timing ........................ 161 pwm timing .................................................... 159 reset, watchdog timer, oscillator start-up timer and power-up timer .............................. 157 timer0 clock timings ...................................... 158 timer1, timer2 and timer3 clock timing ........ 158 usart module, synchronous receive ........... 160 usart module, synchronous transmission ... 160 pic17c43/44 absolute maximum ratings ............................. 175 capture timing ................................................ 188 clkout and i/o timing .................................. 185 dc characteristics ........................................... 177 external clock timing ...................................... 184 memory interface read timing ........................ 191 memory interface write timing ........................ 190 parameter measurement information .............. 183 reset, watchdog timer, oscillator start-up timer and power-up timer timing .................. 186 timer0 clock timing ........................................ 187 timer1, timer2 and timer3 clock timing ........ 187 timing parameter symbology .......................... 182 usart module synchronous receive timing .............................................................. 189 usart module synchronous transmission timing .............................................................. 189 eprom memory access time order suffix ...................... 31 extended microcontroller ................................................... 29 extended microcontroller mode ......................................... 31 external memory interface ................................................. 31 external program memory waveforms .............................. 31 f family of devices ................................................................. 6 pic14000 .................................................................. 213 pic16c5x ................................................................ 214 pic16cxxx .............................................................. 215 pic16c6x ................................................................ 216 pic16c7x ................................................................ 217 pic16c8x ................................................................ 218 pic16c9xx............................................................... 219 pic17cxx ................................................................ 220 ferr ........................................................................... 84, 91 fosc0 ............................................................................... 99 fosc1 ............................................................................... 99 fs0 .................................................................................... 36 fs1 .................................................................................... 36 fs2 .................................................................................... 36 fs3 .................................................................................... 36 fsr0 ............................................................................ 34, 40 fsr1 ............................................................................ 34, 40 fuzzy logic dev. system ( fuzzy tech -mp) .......... 143, 145 g general format for instructions ....................................... 108 general purpose ram ....................................................... 29 general purpose ram bank ............................................. 42 general purpose register (gpr) ...................................... 32 glintd .......................................................... 25, 37, 78, 105 goto .............................................................................. 122 gpr (general purpose register) ...................................... 32 graphs i oh vs. v oh , v dd = 3v ..................................... 170, 200 i oh vs. v oh , v dd = 5v ..................................... 171, 201 i ol vs. v ol , v dd = 3v ...................................... 171, 201 i ol vs. v ol , v dd = 5v ...................................... 172, 202 maximum i dd vs. frequency (external clock 125 c to -40 c) ...................... 167, 197 maximum i pd vs. v dd watchdog disabled ...... 168, 198 maximum i pd vs. v dd watchdog enabled ...... 169, 199 rc oscillator frequency vs. v dd (cext = 100 pf) ........................................ 164, 194 rc oscillator frequency vs. v dd (cext = 22 pf) .......................................... 164, 194 rc oscillator frequency vs. v dd (cext = 300 pf) ........................................ 165, 195 transconductance of lf oscillator vs.v dd ...... 166, 196 transconductance of xt oscillator vs. v dd .... 166, 196 typical i dd vs. frequency (external clock 25 c) ...................................... 167, 197 typical i pd vs. v dd watchdog disabled 25 c . 168, 198 typical i pd vs. v dd watchdog enabled 25 c .. 169, 199 typical rc oscillator vs. temperature ............ 163, 193 v th (input threshold voltage) of i/o pins vs. v dd .................................................................. 172, 202 v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ................ 173, 203 v th , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd ...................................... 173, 203 wdt timer time-out period vs. v dd .............. 170, 200 h hardware multiplier ............................................................ 49 i i/o ports bi-directional .............................................................. 64 i/o ports .................................................................... 53 programming considerations .................................... 64 read-modify-write instructions ................................. 64 successive operations .............................................. 64 incf ................................................................................ 123 incfsnz ......................................................................... 124 incfsz ............................................................................ 123 indf0 .......................................................................... 34, 40 indf1 .......................................................................... 34, 40
1996 microchip technology inc. ds30412c-page 227 pic17c4x indirect addressing indirect addressing .................................................... 39 operation ................................................................... 40 registers .................................................................... 40 initialization conditions for special function registers .... 19 initializing portb .............................................................. 57 initializing portc .............................................................. 58 initializing portd .............................................................. 60 initializing porte .............................................................. 62 instruction flow/pipelining ................................................. 14 instruction set .................................................................. 110 addlw .................................................................... 112 addwf .................................................................... 112 addwfc ................................................................. 113 andlw .................................................................... 113 andwf .................................................................... 114 bcf .......................................................................... 114 bsf .......................................................................... 115 btfsc ..................................................................... 115 btfss ..................................................................... 116 btg .......................................................................... 116 call ........................................................................ 117 clrf ........................................................................ 117 clrwdt .................................................................. 118 comf ...................................................................... 118 cpfseq .................................................................. 119 cpfsgt .................................................................. 119 cpfslt ................................................................... 120 daw ......................................................................... 120 decf ....................................................................... 121 decfsnz ................................................................ 122 decfsz ................................................................... 121 goto ...................................................................... 122 incf ......................................................................... 123 incfsnz ................................................................. 124 incfsz .................................................................... 123 iorlw ..................................................................... 124 iorwf ..................................................................... 125 lcall ...................................................................... 125 movfp .................................................................... 126 movlb .................................................................... 126 movlr .................................................................... 127 movlw ................................................................... 127 movpf .................................................................... 128 movwf ................................................................... 128 mullw .................................................................... 129 mulwf .................................................................... 129 negw ...................................................................... 130 nop ......................................................................... 130 retfie .................................................................... 131 retlw .................................................................... 131 return .................................................................. 132 rlcf ........................................................................ 132 rlncf ..................................................................... 133 rrcf ....................................................................... 133 rrncf .................................................................... 134 setf ........................................................................ 134 sleep ..................................................................... 135 sublw .................................................................... 135 subwf .................................................................... 136 subwfb .................................................................. 136 swapf .................................................................... 137 tablrd ........................................................... 137, 138 tablwt .......................................................... 138, 139 tlrd ........................................................................ 139 tlwt ....................................................................... 140 tstfsz ....................................................................140 xorlw ....................................................................141 xorwf ....................................................................141 instruction set summary ..................................................107 int pin ................................................................................26 inte ...................................................................................22 intedg ........................................................................38, 67 interrupt on change feature ..............................................55 interrupt status register (intsta) ....................................22 interrupts context saving ...........................................................27 flag bits tmr1ie ..............................................................21 tmr1if ..............................................................21 tmr2ie ..............................................................21 tmr2if ..............................................................21 tmr3ie ..............................................................21 tmr3if ..............................................................21 interrupts ....................................................................21 logic ...........................................................................21 operation ....................................................................25 peripheral interrupt enable .........................................23 peripheral interrupt request ......................................24 pwm ...........................................................................76 status register ...........................................................22 table write interaction ...............................................45 timing .........................................................................26 vectors peripheral interrupt .............................................26 ra0/int interrupt ...............................................26 t0cki interrupt ...................................................26 tmr0 interrupt ...................................................26 vectors/priorities ........................................................25 wake-up from sleep ..............................................105 intf ....................................................................................22 intsta ...............................................................................34 intsta register ................................................................22 iorlw ..............................................................................124 iorwf ..............................................................................125 l lcall ...............................................................................125 long writes ........................................................................45 m memory external interface .......................................................31 external memory waveforms .....................................31 memory map (different modes) ..................................30 mode memory access ................................................30 organization ...............................................................29 program memory ........................................................29 program memory map ................................................29 microcontroller ....................................................................29 microprocessor ...................................................................29 minimizing current consumption .....................................106 movfp .............................................................................126 movlb .............................................................................126 movlr .............................................................................127 movlw ............................................................................127 movpf .............................................................................128 movwf ............................................................................128 mpasm assembler ..................................................143, 144
pic17c4x ds30412c-page 228 1996 microchip technology inc. mp-c c compiler ............................................................. 145 mpsim software simulator ...................................... 143, 145 mullw ............................................................................ 129 multiply examples 16 x 16 routine .......................................................... 50 16 x 16 signed routine .............................................. 51 8 x 8 routine .............................................................. 49 8 x 8 signed routine .................................................. 49 mulwf ............................................................................ 129 n negw .............................................................................. 130 nop ................................................................................. 130 o oerr ................................................................................. 84 opcode field descriptions ............................................... 107 osc selection .................................................................... 99 oscillator configuration ............................................................ 100 crystal ...................................................................... 100 external clock .......................................................... 101 external crystal circuit ............................................ 102 external parallel resonant crystal circuit ............... 102 external series resonant crystal circuit ................. 102 rc ............................................................................ 102 rc frequencies ............................................... 165, 195 oscillator start-up time (figure) ........................................ 18 oscillator start-up timer (ost) ................................... 15, 99 ost .............................................................................. 15, 99 ov .................................................................................. 9, 36 overflow (ov) ...................................................................... 9 p package marking information .......................................... 210 packaging information ..................................................... 205 parameter measurement information .............................. 154 pc (program counter) ....................................................... 41 pch .................................................................................... 41 pcl ...................................................................... 34, 41, 108 pclath ....................................................................... 34, 41 pd .............................................................................. 37, 105 peie ............................................................................. 22, 78 peif ................................................................................... 22 peripheral bank .................................................................. 42 peripheral interrupt enable ................................................ 23 peripheral interrupt request (pir) ..................................... 24 picdem-1 low-cost pic16/17 demo board ........... 143, 144 picdem-2 low-cost pic16cxx demo board ........ 143, 144 picdem-3 low-cost pic16c9xxx demo board ............ 144 picmaster rt in-circuit emulator ............................. 143 picstart low-cost development system .................. 143 pie ............................................................. 19, 34, 92, 96, 98 pin compatible devices ................................................... 221 pir ............................................................. 19, 34, 92, 96, 98 pm0 ............................................................................ 99, 106 pm1 ............................................................................ 99, 106 pop .............................................................................. 27, 39 por ............................................................................. 15, 99 porta ................................................................... 19, 34, 53 portb ................................................................... 19, 34, 55 portc ................................................................... 19, 34, 58 portd .................................................................. 19, 34, 60 porte .................................................................. 19, 34, 62 power-down mode ........................................................... 105 power-on reset (por) ................................................ 15, 99 power-up timer (pwrt) ............................................. 15, 99 pr1 .............................................................................. 20, 35 pr2 .............................................................................. 20, 35 pr3/ca1h ......................................................................... 20 pr3/ca1l .......................................................................... 20 pr3h/ca1h ....................................................................... 35 pr3l/ca1l ........................................................................ 35 prescaler assignments ...................................................... 69 pro mate universal programmer ............................... 143 prodh .............................................................................. 20 prodl .............................................................................. 20 program counter (pc) ....................................................... 41 program memory external access waveforms ...................................... 31 external connection diagram .................................... 31 map ............................................................................ 29 modes extended microcontroller ................................... 29 microcontroller ................................................... 29 microprocessor .................................................. 29 protected microcontroller ................................... 29 operation ................................................................... 29 organization .............................................................. 29 transfers from data memory ..................................... 43 protected microcontroller ................................................... 29 ps0 .............................................................................. 38, 67 ps1 .............................................................................. 38, 67 ps2 .............................................................................. 38, 67 ps3 .............................................................................. 38, 67 push ........................................................................... 27, 39 pw1dch ..................................................................... 20, 35 pw1dcl ...................................................................... 20, 35 pw2dch ..................................................................... 20, 35 pw2dcl ...................................................................... 20, 35 pwm ............................................................................ 71, 75 duty cycle ................................................................. 76 external clock source ............................................... 76 frequency vs. resolution .......................................... 76 interrupts ................................................................... 76 max resolution/frequency for external clock input ................................................................. 77 output ........................................................................ 75 periods ...................................................................... 76 pwm1 ................................................................................ 72 pwm1on ..................................................................... 72, 75 pwm2 ................................................................................ 72 pwm2on ..................................................................... 72, 75 pwrt .......................................................................... 15, 99 r ra1/t0cki pin ................................................................... 67 rbie .................................................................................. 23 rbif ................................................................................... 24 rbpu ................................................................................. 55 rc oscillator .................................................................... 102 rc oscillator frequencies ....................................... 165, 195 rcie .................................................................................. 23 rcif .................................................................................. 24 rcreg ................................................ 19, 34, 91, 92, 96, 97 rcsta ....................................................... 19, 34, 92, 96, 98 reading 16-bit value ......................................................... 69
1996 microchip technology inc. ds30412c-page 229 pic17c4x receive status and control register ................................. 83 register file map ............................................................... 33 registers alusta ............................................................... 27, 36 brg ........................................................................... 86 bsr ............................................................................ 27 cpusta .................................................................... 37 file map ..................................................................... 33 fsr0 .......................................................................... 40 fsr1 .......................................................................... 40 indf0 ......................................................................... 40 indf1 ......................................................................... 40 intsta ...................................................................... 22 pie ............................................................................. 23 pir ............................................................................. 24 rcsta ....................................................................... 84 special function table .............................................. 34 t0sta .................................................................. 38, 67 tcon1 ....................................................................... 71 tcon2 ....................................................................... 72 tmr1 ......................................................................... 81 tmr2 ......................................................................... 81 tmr3 ......................................................................... 81 txsta ....................................................................... 83 wreg ........................................................................ 27 reset section ....................................................................... 15 status bits and their significance ............................. 16 time-out in various situations .................................. 16 time-out sequence ................................................... 16 retfie ............................................................................ 131 retlw ............................................................................ 131 return .......................................................................... 132 rlcf ................................................................................ 132 rlncf ............................................................................. 133 rrcf ............................................................................... 133 rrncf ............................................................................ 134 rx pin sampling scheme .................................................. 91 rx9 .................................................................................... 84 rx9d ................................................................................. 84 s sampling ............................................................................ 91 saving status and wreg in ram ................................. 27 setf ................................................................................ 134 sfr .................................................................................. 108 sfr (special function registers) ................................ 29, 32 sfr as source/destination ............................................. 108 signed math ......................................................................... 9 sleep ............................................................... 99, 105, 135 software simulator (mpsim) ........................................... 145 spbrg ...................................................... 19, 34, 92, 96, 98 special features of the cpu ............................................. 99 special function registers ............................ 29, 32, 34, 108 spen ................................................................................. 84 sren ................................................................................. 84 stack operation ................................................................... 39 pointer ........................................................................ 39 stack .......................................................................... 29 stkal ................................................................................ 39 stkav ............................................................................... 37 sublw ............................................................................ 135 subwf ............................................................................ 136 subwfb .......................................................................... 136 swapf .............................................................................137 sync ..................................................................................83 synchronous master mode .................................................93 synchronous master reception .........................................95 synchronous master transmission ....................................93 synchronous slave mode ...................................................97 t t0cki pin ...........................................................................26 t0ckie ...............................................................................22 t0ckif ...............................................................................22 t0cs ............................................................................38, 67 t0ie ....................................................................................22 t0if ....................................................................................22 t0se .............................................................................38, 67 t0sta ..........................................................................34, 38 t16 .....................................................................................71 table latch .........................................................................40 table pointer ......................................................................40 table read example ......................................................................48 section ........................................................................43 table reads section ..................................................48 tablrd operation .....................................................44 timing .........................................................................48 tlrd ..........................................................................48 tlrd operation .........................................................44 table write code ...........................................................................46 interaction ...................................................................45 section ........................................................................43 tablwt operation ....................................................43 terminating long writes ............................................45 timing .........................................................................46 tlwt operation .........................................................43 to external memory ...................................................46 to internal memory ....................................................45 tablrd .............................................................44, 137, 138 tablwt .............................................................43, 138, 139 tblath ..............................................................................40 tblatl ..............................................................................40 tblptrh .....................................................................34, 40 tblptrl ......................................................................34, 40 tclk12 ..............................................................................71 tclk3 ................................................................................71 tcon1 .........................................................................20, 35 tcon2 .........................................................................20, 35 terminating long writes ....................................................45 time-out sequence ...........................................................16 timer resources ................................................................65 timer0 ................................................................................67 timer1 16-bit mode .................................................................74 clock source select ...................................................71 on bit ..........................................................................72 section ..................................................................71, 73 timer2 16-bit mode .................................................................74 clock source select ...................................................71 on bit ..........................................................................72 section ..................................................................71, 73 timer3 clock source select ...................................................71 on bit ..........................................................................72 section ..................................................................71, 77
pic17c4x ds30412c-page 230 1996 microchip technology inc. timing diagrams asynchronous master transmission .......................... 90 asynchronous reception ........................................... 92 back to back asynchronous master transmission .... 90 interrupt (int, tmr0 pins) ......................................... 26 pic17c42 capture ................................................... 159 pic17c42 clkout and i/o .................................... 156 pic17c42 memory interface read .......................... 162 pic17c42 memory interface write .......................... 161 pic17c42 pwm timing ........................................... 159 pic17c42 reset, watchdog timer, oscillator start-up timer and power-up timer ........................ 157 pic17c42 timer0 clock .......................................... 158 pic17c42 timer1, timer2 and timer3 clock .......... 158 pic17c42 usart module, synchronous receive .................................................................... 160 pic17c42 usart module, synchronous transmission ............................................................ 160 pic17c43/44 capture timing .................................. 188 pic17c43/44 clkout and i/o ............................... 185 pic17c43/44 external clock ................................... 184 pic17c43/44 memory interface read ..................... 191 pic17c43/44 memory interface write ..................... 190 pic17c43/44 pwm timing ...................................... 188 pic17c43/44 reset, watchdog timer, oscillator start-up timer and power-up timer ........................ 186 pic17c43/44 timer0 clock ..................................... 187 pic17c43/44 timer1, timer2 and timer3 clock ..... 187 pic17c43/44 usart module synchronous receive .................................................................... 189 pic17c43/44 usart module synchronous transmission ............................................................ 189 synchronous reception ............................................. 95 synchronous transmission ........................................ 94 table read ................................................................ 48 table write ................................................................. 46 tmr0 ................................................................... 68, 69 tmr0 read/write in timer mode .............................. 70 tmr1, tmr2, and tmr3 in external clock mode ..... 80 tmr1, tmr2, and tmr3 in timer mode ................... 81 wake-up from sleep ............................................. 105 timing diagrams and specifications ................................ 155 timing parameter symbology .......................................... 153 tlrd .......................................................................... 44, 139 tlwt ......................................................................... 43, 140 tmr0 16-bit read ................................................................ 69 16-bit write ................................................................. 69 clock timing ............................................................ 158 module ....................................................................... 68 operation ................................................................... 68 overview .................................................................... 65 prescaler assignments .............................................. 69 read/write considerations ........................................ 69 read/write in timer mode ......................................... 70 timing .................................................................. 68, 69 tmr0 status/control register (t0sta) ......................... 38 tmr0h ............................................................................... 34 tmr0l ............................................................................... 34 tmr1 ........................................................................... 20, 35 8-bit mode .................................................................. 73 external clock input ................................................... 73 overview .................................................................... 65 timer mode ................................................................ 81 timing in external clock mode .................................. 80 two 8-bit timer/counter mode .................................. 73 using with pwm ........................................................ 75 tmr1cs ............................................................................ 71 tmr1ie .............................................................................. 23 tmr1if .............................................................................. 24 tmr1on ............................................................................ 72 tmr2 ........................................................................... 20, 35 8-bit mode .................................................................. 73 external clock input .................................................. 73 in timer mode ........................................................... 81 timing in external clock mode .................................. 80 two 8-bit timer/counter mode .................................. 73 using with pwm ........................................................ 75 tmr2cs ............................................................................ 71 tmr2ie .............................................................................. 23 tmr2if .............................................................................. 24 tmr2on ............................................................................ 72 tmr3 dual capture1 register mode ................................... 79 example, reading from ............................................ 80 example, writing to .................................................. 80 external clock input .................................................. 80 in timer mode ........................................................... 81 one capture and one period register mode ........... 78 overview .................................................................... 65 reading/writing ......................................................... 80 timing in external clock mode .................................. 80 tmr3cs ...................................................................... 71, 77 tmr3h ........................................................................ 20, 35 tmr3ie .............................................................................. 23 tmr3if ........................................................................ 24, 77 tmr3l ......................................................................... 20, 35 tmr3on ...................................................................... 72, 77 to ...................................................................... 37, 103, 105 transmit status and control register ................................ 83 trmt ................................................................................. 83 tstfsz ........................................................................... 140 turning on 16-bit timer ..................................................... 74 tx9 .................................................................................... 83 tx9d .................................................................................. 83 txen ................................................................................. 83 txie ................................................................................... 23 txif ................................................................................... 24 txreg ................................................ 19, 34, 89, 93, 97, 98 txsta ....................................................... 19, 34, 92, 96, 98 u upward compatibility ........................................................... 5 usart asynchronous master transmission ......................... 90 asynchronous mode .................................................. 89 asynchronous receive .............................................. 91 asynchronous transmitter ......................................... 89 baud rate generator ................................................ 86 synchronous master mode ........................................ 93 synchronous master reception ................................ 95 synchronous master transmission ........................... 93 synchronous slave mode .......................................... 97 synchronous slave transmit ..................................... 97 w wake-up from sleep ...................................................... 105 wake-up from sleep through interrupt ......................... 105 watchdog timer ........................................................ 99, 103
1996 microchip technology inc. ds30412c-page 231 pic17c4x wdt ........................................................................... 99, 103 clearing the wdt .................................................... 103 normal timer ........................................................... 103 period ....................................................................... 103 programming considerations .................................. 103 wdtps0 ............................................................................ 99 wdtps1 ............................................................................ 99 wreg ................................................................................ 34 x xorlw ............................................................................ 141 xorwf ............................................................................ 141 z z ..................................................................................... 9, 36 zero (z) ................................................................................ 9 list of examples example 3-1: signed math ..................................................9 example 3-2: instruction pipeline flow .............................14 example 5-1: saving status and wreg in ram ..........27 example 6-1: indirect addressing......................................40 example 7-1: table write ..................................................46 example 7-2: table read..................................................48 example 8-1: 8 x 8 multiply routine ..................................49 example 8-2: 8 x 8 signed multiply routine......................49 example 8-3: 16 x 16 multiply routine ..............................50 example 8-4: 16 x 16 signed multiply routine..................51 example 9-1: initializing portb .......................................57 example 9-2: initializing portc .......................................58 example 9-3: initializing portd .......................................60 example 9-4: initializing porte .......................................62 example 9-5: read modify write instructions on an i/o port ........................................................64 example 11-1: 16-bit read .................................................69 example 11-2: 16-bit write..................................................69 example 12-1: sequence to read capture registers.........78 example 12-2: writing to tmr3 ..........................................80 example 12-3: reading from tmr3 ....................................80 example 13-1: calculating baud rate error........................86 example f-1: pic17c42 to sleep....................................223 list of figures figure 3-1: pic17c42 block diagram ...........................10 figure 3-2: pic17cr42/42a/43/r43/44 block diagram.......................................................11 figure 3-3: clock/instruction cycle................................14 figure 4-1: simplified block diagram of on-chip reset circuit................................................15 figure 4-2: time-out sequence on power-up (mclr tied to v dd ) ....................................17 figure 4-3: time-out sequence on power-up (mclr not tied to v dd )............................17 figure 4-4: slow rise time (mclr tied to v dd ) ..........17 figure 4-5: oscillator start-up time ..............................18 figure 4-6: using on-chip por ....................................18 figure 4-7: brown-out protection circuit 1.....................18 figure 4-8: pic17c42 external power-on reset circuit (for slow v dd power-up) ................18 figure 4-9: brown-out protection circuit 2.....................18 figure 5-1: interrupt logic .............................................21 figure 5-2: intsta register (address: 07h, unbanked)...................................................22 figure 5-3: pie register (address: 17h, bank 1) ..........23 figure 5-4: pir register (address: 16h, bank 1) ..........24 figure 5-5: int pin / t0cki pin interrupt timing...........26 figure 6-1: program memory map and stack................29 figure 6-2: memory map in different modes .................30 figure 6-3: external program memory access waveforms ..................................................31 figure 6-4: typical external program memory connection diagram....................................31 figure 6-5: pic17c42 register file map.......................33 figure 6-6: pic17cr42/42a/43/r43/44 register file map.......................................................33 figure 6-7: alusta register (address: 04h, unbanked)...................................................36 figure 6-8: cpusta register (address: 06h, unbanked)...................................................37 figure 6-9: t0sta register (address: 05h, unbanked)...................................................38 figure 6-10: indirect addressing......................................39 figure 6-11: program counter operation ........................41
pic17c4x ds30412c-page 232 1996 microchip technology inc. figure 6-12: program counter using the call and goto instructions...................................... 41 figure 6-13: bsr operation (pic17c43/r43/44) ........... 42 figure 7-1: tlwt instruction operation........................ 43 figure 7-2: tablwt instruction operation................... 43 figure 7-3: tlrd instruction operation ........................ 44 figure 7-4: tablrd instruction operation ................... 44 figure 7-5: tablwt write timing (external memory) ...................................... 46 figure 7-6: consecutive tablwt write timing (external memory) ...................................... 47 figure 7-7: tablrd timing.......................................... 48 figure 7-8: tablrd timing (consecutive tablrd instructions) ................................................ 48 figure 9-1: ra0 and ra1 block diagram ..................... 53 figure 9-2: ra2 and ra3 block diagram ..................... 54 figure 9-3: ra4 and ra5 block diagram ..................... 54 figure 9-4: block diagram of rb<7:4> and rb<1:0> port pins ..................................................... 55 figure 9-5: block diagram of rb3 and rb2 port pins.. 56 figure 9-6: block diagram of rc<7:0> port pins ......... 58 figure 9-7: portd block diagram (in i/o port mode) ....................................... 60 figure 9-8: porte block diagram (in i/o port mode) ....................................... 62 figure 9-9: successive i/o operation ........................... 64 figure 11-1: t0sta register (address: 05h, unbanked) .................................................. 67 figure 11-2: timer0 module block diagram ................... 68 figure 11-3: tmr0 timing with external clock (increment on falling edge) ....................... 68 figure 11-4: tmr0 timing: write high or low byte ....... 69 figure 11-5: tmr0 read/write in timer mode ............... 70 figure 12-1: tcon1 register (address: 16h, bank 3) ... 71 figure 12-2: tcon2 register (address: 17h, bank 3) ... 72 figure 12-3: timer1 and timer2 in two 8-bit timer/counter mode................................... 73 figure 12-4: tmr1 and tmr2 in 16-bit timer/counter mode........................................................... 74 figure 12-5: simplified pwm block diagram .................. 75 figure 12-6: pwm output ............................................... 75 figure 12-7: timer3 with one capture and one period register block diagram................... 78 figure 12-8: timer3 with two capture registers block diagram ............................................ 79 figure 12-9: tmr1, tmr2, and tmr3 operation in external clock mode................................... 80 figure 12-10: tmr1, tmr2, and tmr3 operation in timer mode................................................. 81 figure 13-1: txsta register (address: 15h, bank 0) .... 83 figure 13-2: rcsta register (address: 13h, bank 0) ... 84 figure 13-3: usart transmit......................................... 85 figure 13-4: usart receive.......................................... 85 figure 13-5: asynchronous master transmission........... 90 figure 13-6: asynchronous master transmission (back to back) ............................................ 90 figure 13-7: rx pin sampling scheme .......................... 91 figure 13-8: asynchronous reception............................ 92 figure 13-9: synchronous transmission ........................ 94 figure 13-10: synchronous transmission (through txen) ......................................... 94 figure 13-11: synchronous reception (master mode, sren)......................................................... 95 figure 14-1: configuration word..................................... 99 figure 14-2: crystal or ceramic resonator operation (xt or lf osc configuration) .................. 100 figure 14-3: crystal operation, overtone crystals (xt osc configuration) ........................... 101 figure 14-4: external clock input operation (ec osc configuration)........................... 101 figure 14-5: external parallel resonant crystal oscillator circuit ....................................... 102 figure 14-6: external series resonant crystal oscillator circuit ....................................... 102 figure 14-7: rc oscillator mode .................................. 102 figure 14-8: watchdog timer block diagram............... 104 figure 14-9: wake-up from sleep through interrupt... 105 figure 15-1: general format for instructions................ 108 figure 15-2: q cycle activity ........................................ 109 figure 17-1: parameter measurement information....... 154 figure 17-2: external clock timing .............................. 155 figure 17-3: clkout and i/o timing .......................... 156 figure 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ........................... 157 figure 17-5: timer0 clock timings............................... 158 figure 17-6: timer1, timer2, and timer3 clock timings..................................................... 158 figure 17-7: capture timings ....................................... 159 figure 17-8: pwm timings ........................................... 159 figure 17-9: usart module: synchronous transmission (master/slave) timing ........ 160 figure 17-10: usart module: synchronous receive (master/slave) timing .............................. 160 figure 17-11: memory interface write timing ................ 161 figure 17-12: memory interface read timing ................ 162 figure 18-1: typical rc oscillator frequency vs. temperature ....................................... 163 figure 18-2: typical rc oscillator frequency vs. v dd ..................................................... 164 figure 18-3: typical rc oscillator frequency vs. v dd ..................................................... 164 figure 18-4: typical rc oscillator frequency vs. v dd ..................................................... 165 figure 18-5: transconductance (gm) of lf oscillator vs. v dd ..................................................... 166 figure 18-6: transconductance (gm) of xt oscillator vs. v dd ..................................................... 166 figure 18-7: typical i dd vs. frequency (external clock 25 c) .............................................. 167 figure 18-8: maximum i dd vs. frequency (external clock 125 c to -40 c) .............................. 167 figure 18-9: typical i pd vs. v dd watchdog disabled 25 c .......................................... 168 figure 18-10: maximum i pd vs. v dd watchdog disabled ................................................... 168 figure 18-11: typical i pd vs. v dd watchdog enabled 25 c ........................................... 169 figure 18-12: maximum i pd vs. v dd watchdog enabled .................................................... 169 figure 18-13: wdt timer time-out period vs. v dd ...... 170 figure 18-14: i oh vs. v oh , v dd = 3v.............................. 170 figure 18-15: i oh vs. v oh , v dd = 5v.............................. 171 figure 18-16: i ol vs. v ol , v dd = 3v............................... 171 figure 18-17: i ol vs. v ol , v dd = 5v............................... 172 figure 18-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd ............................. 172 figure 18-19: v th , v il of i/o pins (schmitt trigger) vs . v dd ........................................................... 173 figure 18-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd ........ 173 figure 19-1: parameter measurement information....... 183
1996 microchip technology inc. ds30412c-page 233 pic17c4x figure 19-2: external clock timing............................... 184 figure 19-3: clkout and i/o timing........................... 185 figure 19-4: reset, watchdog timer, oscillator start-up timer, and power-up timer timing............................ 186 figure 19-5: timer0 clock timings ............................... 187 figure 19-6: timer1, timer2, and timer3 clock timings ..................................................... 187 figure 19-7: capture timings ....................................... 188 figure 19-8: pwm timings ........................................... 188 figure 19-9: usart module: synchronous transmission (master/slave) timing ........ 189 figure 19-10: usart module: synchronous receive (master/slave) timing................. 189 figure 19-11: memory interface write timing (not supported in pic17lc4x devices)... 190 figure 19-12: memory interface read timing (not supported in pic17lc4x devices)... 191 figure 20-1: typical rc oscillator frequency vs. temperature ............................................. 193 figure 20-2: typical rc oscillator frequency vs. v dd ...................................................... 194 figure 20-3: typical rc oscillator frequency vs. v dd ...................................................... 194 figure 20-4: typical rc oscillator frequency vs. v dd ...................................................... 195 figure 20-5: transconductance (gm) of lf oscillator vs. v dd ...................................................... 196 figure 20-6: transconductance (gm) of xt oscillator vs. v dd ...................................................... 196 figure 20-7: typical i dd vs. frequency (external clock 25 c)............................................... 197 figure 20-8: maximum i dd vs. frequency (external clock 125 c to -40 c) .............................. 197 figure 20-9: typical i pd vs. v dd watchdog disabled 25 c........................................... 198 figure 20-10: maximum i pd vs. v dd watchdog disabled.................................................... 198 figure 20-11: typical i pd vs. v dd watchdog enabled 25 c............................................ 199 figure 20-12: maximum i pd vs. v dd watchdog enabled..................................................... 199 figure 20-13: wdt timer time-out period vs. v dd ....... 200 figure 20-14: i oh vs. v oh , v dd = 3v .............................. 200 figure 20-15: i oh vs. v oh , v dd = 5v .............................. 201 figure 20-16: i ol vs. v ol , v dd = 3v ............................... 201 figure 20-17: i ol vs. v ol , v dd = 5v ............................... 202 figure 20-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd .............................. 202 figure 20-19: v th , v il of i/o pins (schmitt trigger) vs . v dd ..................................................... 203 figure 20-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd ........ 203 list of tables table 1-1: pic17cxx family of devices ....................... 6 table 3-1: pinout descriptions..................................... 12 table 4-1: time-out in various situations ................... 16 table 4-2: status bits and their significance .......... 16 table 4-3: reset condition for the program counter and the cpusta register.......................... 16 table 4-4: initialization conditions for special function registers...................................... 19 table 5-1: interrupt vectors/priorities .......................... 25 table 6-1: mode memory access ................................ 30 table 6-2: eprom memory access time ordering suffix ............................................31 table 6-3: special function registers..........................34 table 7-1: interrupt - table write interaction................45 table 8-1: performance comparison ...........................49 table 9-1: porta functions .......................................54 table 9-2: registers/bits associated with porta.......54 table 9-3: portb functions .......................................57 table 9-4: registers/bits associated with portb.......57 table 9-5: portc functions .......................................59 table 9-6: registers/bits associated with portc.......59 table 9-7: portd functions .......................................61 table 9-8: registers/bits associated with portd.......61 table 9-9: porte functions .......................................63 table 9-10: registers/bits associated with porte.......63 table 11-1: registers/bits associated with timer0 ........70 table 12-1: turning on 16-bit timer ..............................74 table 12-2: summary of timer1 and timer2 registers .....................................................74 table 12-3: pwm frequency vs. resolution at 25 mhz ........................................................76 table 12-4: registers/bits associated with pwm ..........77 table 12-5: registers associated with capture .............79 table 12-6: summary of tmr1, tmr2, and tmr3 registers .....................................................81 table 13-1: baud rate formula .....................................86 table 13-2: registers associated with baud rate generator ....................................................86 table 13-3: baud rates for synchronous mode ............87 table 13-4: baud rates for asynchronous mode...........88 table 13-5: registers associated with asynchronous transmission ...............................................90 table 13-6: registers associated with asynchronous reception ....................................................92 table 13-7: registers associated with synchronous master transmission ...................................94 table 13-8: registers associated with synchronous master reception ........................................96 table 13-9: registers associated with synchronous slave transmission .....................................98 table 13-10: registers associated with synchronous slave reception ..........................................98 table 14-1: configuration locations.............................100 table 14-2: capacitor selection for ceramic resonators ................................................101 table 14-3: capacitor selection for crystal oscillator ..................................................101 table 14-4: registers/bits associated with the watchdog timer ........................................104 table 15-1: opcode field descriptions ........................107 table 15-2: pic17cxx instruction set .........................110 table 16-1: development tools from microchip.............146 table 17-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ..........148 table 17-2: external clock timing requirements ........155 table 17-3: clkout and i/o timing requirements....156 table 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements.................157 table 17-5: timer0 clock requirements......................158 table 17-6: timer1, timer2, and timer3 clock requirements ............................................158 table 17-7: capture requirements ..............................159 table 17-8: pwm requirements ..................................159
pic17c4x ds30412c-page 234 1996 microchip technology inc. table 17-9: serial port synchronous transmission requirements ........................................... 160 table 17-10: serial port synchronous receive requirements ........................................... 160 table 17-11: memory interface write requirements ..... 161 table 17-12: memory interface read requirements..... 162 table 18-1: pin capacitance per package type ......... 163 table 18-2: rc oscillator frequencies........................ 165 table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices).......... 176 table 19-2: external clock timing requirements ....... 184 table 19-3: clkout and i/o timing requirements ... 185 table 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements ................ 186 table 19-5: timer0 clock requirements ..................... 187 table 19-6: timer1, timer2, and timer3 clock requirements ........................................... 187 table 19-7: capture requirements.............................. 188 table 19-8: pwm requirements.................................. 188 table 19-9: synchronous transmission requirements ........................................... 189 table 19-10: synchronous receive requirements ....... 189 table 19-11: memory interface write requirements (not supported in pic17lc4x devices)... 190 table 19-12: memory interface read requirements (not supported in pic17lc4x devices)... 191 table 20-1: pin capacitance per package type ......... 193 table 20-2: rc oscillator frequencies........................ 195 table e-1: pin compatible devices............................ 221 list of equations equation 8-1: 16 x 16 unsigned multiplication algorithm..................................................... 50 equation 8-2: 16 x 16 signed multiplication algorithm..................................................... 51
1996 microchip technology inc. ds30412c-page 235 pic17c4x on-line support microchip provides two methods of on-line support. these are the microchip bbs and the microchip world wide web (www) site. use microchip's bulletin board service (bbs) to get current information and help about microchip products. microchip provides the bbs communication channel for you to use in extending your technical staff with micro- controller and memory experts. to provide you with the most responsive service possible, the microchip systems team monitors the bbs, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how microchip products pro- vide project solutions. the web site, like the bbs, is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp.mchip.com/biz/mchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? business information is also available, including listings of microchip sales of?es, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products connecting to the microchip bbs connect worldwide to the microchip bbs using either the internet or the compuserve communications net- work. internet: you can telnet or ftp to the microchip bbs at the address: mchipbbs.microchip.com compuser ve comm unications netw ork: when using the bbs via the compuserve network, in most cases, a local call is your only expense. the microchip bbs connection does not use compuserve membership services, therefore you do not need compuserve membership to join microchip's bbs. there is no charge for connecting to the microchip bbs. the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allow multiple users various baud rates depending on the local point of access. the following connect procedure applies in most loca- tions. 1. set your modem to 8-bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress the key and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress the key and ?ost name: will appear. 5. type mchipbbs, depress the key and you will be connected to the microchip bbs. in the united states, to ?d the compuserve phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with ?ost name:? type network, depress the key and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 723-1550 for your local compuserve number. microchip regularly uses the microchip bbs to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for microchip systems software products. for each sig, a moderator monitors, scans, and approves or disap- proves ?es submitted to the sig. no executable ?es are accepted from the user community in general to limit the spread of computer viruses. systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flexrom, mplab and fuzzylab, are trade- marks and sqtp is a service mark of microchip in the u.s.a. fuzzytech is a registered trademark of inform software corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trade- mark of intel corporation. windows is a trademark and ms-dos, microsoft windows are registered trademarks of microsoft corporation. compuserve is a registered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. 960513 this document was created with framemake r404
pic17c4x ds30412c-page 236 1996 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30412c pic17c4x
1996 microchip technology inc. ds30412c-page 237 pic17c4x pic17c4x pr oduct identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales of?es. sales and support products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1.your local microchip sales ofce (see below) 2.the microchip corporate literature center u.s. fax: (602) 786-7277 3.the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. pattern: qtp, sqtp, rom code (factory speci?d) or special requirements. blank for otp and windowed devices package: p = pdip jw = windowed cerdip p = pdip (600 mil) pq = mqfp pt = tqfp l = plcc temperature = 0?c to +70?c range: i = ?0?c to +85?c frequency 08 = 8 mhz range: 16 = 16 mhz 25 = 25 mhz 33 = 33 mhz device: pic17c44 : standard vdd range pic17c44t : (tape and reel) pic17lc44 : extended vdd range part no. xx x /xx xxx examples a) pic17c42 16/p commercial temp., pdip package, 16 mhz, normal v dd limits b) pic17lc44 08/pt commercial temp., tqfp package, 8mhz, extended v dd limits c) pic17c43 25i/p industrial temp., pdip package, 25 mhz, normal v dd limits this document was created with framemake r404
pic17c4x ds30412c-page 238 1996 microchip technology inc. notes:
pic17c4x ds30412c-page 239 1996 microchip technology inc. notes:
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
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